coreboot-gerrit November 2021

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Change in coreboot[master]: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59527 ) Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads ...................................................................... mb/lenovo: Enable MEI on Sandy Bridge ThinkPads It was already enabled on T520 and L520, but disabled on X220, T420 and T420s. On X220, it was disabled by commit 0793afe9 (mb/lenovo/x220: disable ME). I can't reproduce those issues today on linux 4.4 and linux 5.13. Also, it breaks the me_disable feature, we already have a Kconfig option to hide MEI in case of errors, and it will be hidden on disabled, recovery, firmware update paths anyway. Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59527 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> --- M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Alexander Couzens: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index e42e519..457ccbe 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -61,7 +61,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index ab98ca0..32736a8 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -63,7 +63,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 53eb23a..b239d64 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -60,7 +60,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT -- To view, visit https://review.coreboot.org/c/coreboot/+/59527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Gerrit-Change-Number: 59527 Gerrit-PatchSet: 5 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: guybrush: add RO_GSCVD area to FMAP
by Vadim Bendebury (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Hung-Te Lin, Furquan Shaikh, Mathew King, Paul Menzel, Julius Werner. Vadim Bendebury has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57864 ) Change subject: guybrush: add RO_GSCVD area to FMAP ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57864/comment/b5484a0e_ae2c2def PS1, Line 7: guybrush > mb/google/guybrush Done File src/mainboard/google/guybrush/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/57864/comment/bb55ba13_f7d7a79f PS1, Line 29: RO_GSCVD 8K > RO_VPD will not be part of the things that are verified by GSCVD, so I don't think that extra contai […] Sorry I left this dangling for a while. I thing RO_GSCVD should be part of the RO section, and should be updated only if WP is disabled and the RO is actually updated. It is easy to script specifying the areas to verify, so given the dump_fmap output, so it does not really matter where in the RO space the verification section is. -- To view, visit https://review.coreboot.org/c/coreboot/+/57864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01 Gerrit-Change-Number: 57864 Gerrit-PatchSet: 1 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 16:57:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Vadim Bendebury <vbendeb(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Number Ethernet devices
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58628 ) Change subject: mb/prodrive/hermes: Number Ethernet devices ...................................................................... mb/prodrive/hermes: Number Ethernet devices The Prodrive Hermes mainboard has four i211 Ethernet NICs and an i210 Ethernet NIC, but their numbering isn't consistent with the PCIe root port function numbers. With only a M.2 SSD plugged in, Linux uses the following names: PHY 0 ---> enp6s0 PHY 1 ---> enp4s0 PHY 2 ---> enp3s0 PHY 3 ---> enp1s0 PHY 4 ---> enp2s0 These names change after adding or removing PCIe devices in slots connected to root ports that get enumerated before the NICs' root ports, because the assignment of secondary bus numbers depends on the enumeration order. Because of this, the "predictable" network interface names are not at all predictable, which is awful. To avoid this, describe the NICs using SMBIOS Type41 entries with the correct instance numbers. With this patch, Linux uses these names: PHY 0 ---> eno0 PHY 1 ---> eno1 PHY 2 ---> eno2 PHY 3 ---> eno3 PHY 4 ---> eno4 No matter what PCIe devices are present, these names don't change. Change-Id: I7a527298f84172f9135006083ad7e748dcc27911 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58628 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/prodrive/hermes/Kconfig M src/mainboard/prodrive/hermes/devicetree.cb 2 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index 2fecc06..af07ee1 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -14,6 +14,7 @@ select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_HDA_VERB select ONBOARD_VGA_IS_PRIMARY + select SMBIOS_TYPE41_PROVIDED_BY_DEVTREE select HAVE_ACPI_RESUME if !HERMES_USES_SPS_FIRMWARE select DISABLE_ACPI_HIBERNATE if HERMES_USES_SPS_FIRMWARE diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 8faf016..e0655c5 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -199,18 +199,30 @@ device pci 1c.4 on # PCIe root port 5 (PHY 3) register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" + device pci 00.0 on + smbios_dev_info 3 + end end device pci 1c.5 on # PCIe root port 6 (PHY 4) register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" + device pci 00.0 on + smbios_dev_info 4 + end end device pci 1c.6 on # PCIe root port 7 (PHY 2) register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" + device pci 00.0 on + smbios_dev_info 2 + end end device pci 1c.7 on # PCIe root port 8 (PHY 1) register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + device pci 00.0 on + smbios_dev_info 1 + end end device pci 1d.0 on # PCIe root port 9 (M2 M) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" @@ -221,6 +233,9 @@ device pci 1d.5 on # PCIe root port 14 (PHY 0) register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" + device pci 00.0 on + smbios_dev_info 0 + end end device pci 1d.6 on # PCIe root port 15 (BMC) device pci 00.0 on # Aspeed PCI Bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/58628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a527298f84172f9135006083ad7e748dcc27911 Gerrit-Change-Number: 58628 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/delbin: Add fw_config probe for ALC5682-VD & VS
by Tim Wawrzynczak (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Anson Tseng, Frank Chu, Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59557 ) Change subject: mb/google/volteer/var/delbin: Add fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/volteer/variants/delbin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59557/comment/371dd19a_7897f1cb PS6, Line 148: device i2c 1a on end suggestion: if you add an alias here, you can simplify the variant.c code quite a bit, I will show you. change this to: `device i2c 1a alias audio_codec on end` File src/mainboard/google/volteer/variants/delbin/variant.c: https://review.coreboot.org/c/coreboot/+/59557/comment/dbdb0515_1422376d PS6, Line 7: : extern struct chip_operations drivers_i2c_generic_ops; : static void audio_codec_update(void) : { : const struct device_path codec_path[] = { : {.type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_I2C0}, : {.type = DEVICE_PATH_I2C, .i2c.device = 0x1a} : }; : const struct device *codec = : find_dev_nested_path(pci_root_bus(), codec_path, ARRAY_SIZE(codec_path)); : struct drivers_i2c_generic_config *config; : : if (!codec || (codec->chip_ops != &drivers_i2c_generic_ops) || !codec->chip_info) : return; : config = codec->chip_info; : : if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682))) : config->hid = "10EC5682"; : else if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682I_VS))) : config->hid = "RTL5682"; if you add the alias above, you should be able to simplify this to (untested): ``` static void audio_codec_update(void) { const struct device *codec = DEV_PTR(audio_codec); struct drivers_i2c_generic_config *config; config = codec->chip_info; if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682))) config->hid = "10EC5682"; else config->hid = "RTL5682"; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/59557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieef638f78edd3428e572a76f06fb9c8757278971 Gerrit-Change-Number: 59557 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Anson Tseng <ansontseng(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 23 Nov 2021 16:56:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell/optiplex_9010/devicetree.cb: Enable missing GPEs
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59526 ) Change subject: mb/dell/optiplex_9010/devicetree.cb: Enable missing GPEs ...................................................................... mb/dell/optiplex_9010/devicetree.cb: Enable missing GPEs Enable PCI_EXP_EN, PME_EN and PME_B0_EN GPEs used for PCI devices. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I4480921a294f35a0dfe1e5acd90d55f6fb4c85b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59526 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/dell/optiplex_9010/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb index ec585b9..fd95081 100644 --- a/src/mainboard/dell/optiplex_9010/devicetree.cb +++ b/src/mainboard/dell/optiplex_9010/devicetree.cb @@ -20,7 +20,7 @@ device pci 06.0 off end # PEG2 chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "gpe0_en" = "0x00000146" + register "gpe0_en" = "0x00002a46" register "alt_gp_smi_en" = "0x0004" register "gpi2_routing" = "1" register "gpi12_routing" = "2" -- To view, visit https://review.coreboot.org/c/coreboot/+/59526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4480921a294f35a0dfe1e5acd90d55f6fb4c85b4 Gerrit-Change-Number: 59526 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/dell/optiplex_9010/Kconfig: Select Super I/O UART availability
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59522 ) Change subject: mb/dell/optiplex_9010/Kconfig: Select Super I/O UART availability ...................................................................... mb/dell/optiplex_9010/Kconfig: Select Super I/O UART availability Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie1b270d49660fd60b6a91194167467c4453e1b6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59522 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/dell/optiplex_9010/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/dell/optiplex_9010/Kconfig b/src/mainboard/dell/optiplex_9010/Kconfig index ac0912b..90d4b84 100644 --- a/src/mainboard/dell/optiplex_9010/Kconfig +++ b/src/mainboard/dell/optiplex_9010/Kconfig @@ -19,6 +19,7 @@ select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select PCIEXP_L1_SUB_STATE + select DRIVERS_UART_8250IO config MAINBOARD_DIR default "dell/optiplex_9010" -- To view, visit https://review.coreboot.org/c/coreboot/+/59522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1b270d49660fd60b6a91194167467c4453e1b6b Gerrit-Change-Number: 59522 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/gpio: drop unused gpio_get_address
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

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Change in coreboot[master]: soc/amd/common/acpi/gpio_bank_lib: drop unused methods
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59598 ) Change subject: soc/amd/common/acpi/gpio_bank_lib: drop unused methods ...................................................................... soc/amd/common/acpi/gpio_bank_lib: drop unused methods Those methods were only in the non-common Stoneyridge GPIO ACPI code that got dropped, so drop those unused methods too. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2 --- M src/soc/amd/common/acpi/gpio_bank_lib.asl 1 file changed, 0 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/59598/1 diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 579ff68..eba263e 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -36,90 +36,6 @@ TEMP = Arg1 } -Method (GPGB, 0x2) -{ - /* - * Returns the desired byte - * Arg0 - GPIO pin control MMIO address - * Arg1 - Desired byte (0 through 3) - */ - Local2 = Arg1 * 8 - Return ((GPRD (Arg0) >> Local2) & 0x000000FF) -} - -Method (GPSB, 0x3) -{ - /* - * Reads dword, replace byte, write back dword - * Arg0 - GPIO pin control MMIO address - * Arg1 - Desired byte (0 through 3) - * Arg2 - Value - */ - Local2 = Arg1 * 8 - Local3 = (GPRD(Arg0) >> Local2) & 0xFFFFFF00 - Local4 = ((Arg2 & 0x000000FF) | Local3) << Local2 - GPWR (Arg0, Local4) -} - -/* Read pin control byte 0 */ -Method (GPR0, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 0)) -} - -/* Read pin control byte 1 */ -Method (GPR1, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 1)) -} - -/* Read pin control byte 2 */ -Method (GPR2, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 2)) -} - -/* Read pin control byte 3 */ -Method (GPR3, 0x1) -{ - Return (GPGB(Arg0, 3)) -} - -/* Write pin control byte 0 */ -Method (GPW0, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 0, Arg1) -} - -/* Write pin control byte 1 */ -Method (GPW1, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 1, Arg1) -} - -/* Write pin control byte 2 */ -Method (GPW2, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 2, Arg1) -} - -/* Write pin control byte 3 */ -Method (GPW3, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 3, Arg1) -} - /* * Set GPIO Output Value * Arg0 - GPIO Number -- To view, visit https://review.coreboot.org/c/coreboot/+/59598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2 Gerrit-Change-Number: 59598 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: drop unused GPIO_PIN_IN/OUT
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

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Change in coreboot[master]: soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO
by Felix Held (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59596 ) Change subject: soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO ...................................................................... soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO Stoneyridge uses the same GPIO bank peripheral as Picasso and Cezanne so we can use the common AMD SoC GPIO ACPI code. TEST=none Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/acpi.c 2 files changed, 1 insertion(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/59596/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 50e66b0..769a615 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -24,6 +24,7 @@ select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_AOAC diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index b2de89e..7596c9f 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -157,103 +157,3 @@ acpigen_write_name_integer("PCNT", cores); acpigen_pop_len(); } - -static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) -{ - /* - * Store (\_SB.GPR2 (addr), Local5) - * \_SB.GPR2 is used to read control byte 2 from control register. - * / It is defined in gpio_lib.asl. - */ - acpigen_write_store(); - acpigen_emit_namestring("\\_SB.GPR2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); -} - -static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - uintptr_t addr = gpio_get_address(gpio_num); - - acpigen_soc_get_gpio_in_local5(addr); - - /* If (And (Local5, mask)) */ - acpigen_write_if_and(LOCAL5_OP, mask); - - /* Store (One, Local0) */ - acpigen_write_store_ops(ONE_OP, LOCAL0_OP); - - /* Else */ - acpigen_write_else(); - - /* Store (Zero, Local0) */ - acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); - - acpigen_pop_len(); /* Else */ - - return 0; -} - -static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - uintptr_t addr = gpio_get_address(gpio_num); - - /* Store (0x40, Local0) */ - acpigen_write_store(); - acpigen_write_integer(GPIO_PIN_OUT); - acpigen_emit_byte(LOCAL0_OP); - - acpigen_soc_get_gpio_in_local5(addr); - - if (val) { - /* Or (Local5, GPIO_PIN_OUT, Local5) */ - acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); - } else { - /* Not (GPIO_PIN_OUT, Local6) */ - acpigen_write_not(LOCAL0_OP, LOCAL6_OP); - - /* And (Local5, Local6, Local5) */ - acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); - } - - /* - * SB.GPW2 (addr, Local5) - * \_SB.GPW2 is used to write control byte in control register - * / byte 2. It is defined in gpio_lib.asl. - */ - acpigen_emit_namestring("\\_SB.GPW2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); - - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_set_gpio_val(gpio_num, 1); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_set_gpio_val(gpio_num, 0); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/59596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a Gerrit-Change-Number: 59596 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021