coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: libpayload: Add mock assert support for unit testing purposes
by Jakub Czapiga (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Jakub Czapiga. Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59495 to look at the new patch set (#3). Change subject: libpayload: Add mock assert support for unit testing purposes ...................................................................... libpayload: Add mock assert support for unit testing purposes Some unit tests might require catching assert failures. This patch adds an assert() variant depending on __TEST__ define passed to unit tests. Change-Id: I7e4620400f27dbebc57c71bbf2bf9144ca65807f Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M payloads/libpayload/include/assert.h 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59495/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e4620400f27dbebc57c71bbf2bf9144ca65807f Gerrit-Change-Number: 59495 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/var/kano: set power limits for thermal
by Sumeet R Pawnikar (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: David Wu. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59091 ) Change subject: mb/google/brya/var/kano: set power limits for thermal ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19 Gerrit-Change-Number: 59091 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 23 Nov 2021 12:42:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: elogtool: Add a subtype under Chrome OS diagnostics event
by Hsuan-ting Chen (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Hsuan Ting Chen. Hello Hsuan Ting Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59578 to review the following change. Change subject: elogtool: Add a subtype under Chrome OS diagnostics event ...................................................................... elogtool: Add a subtype under Chrome OS diagnostics event Add a subtype under Chrome OS diagnostics events: * ELOG_CROS_UPLOAD(0x00): sub-type for marking the metrics for Chrome OS diagnostics is uploaded to UMA services. This event will be added in Chrome OS with elogtool since we could only upload to UMA there. Change-Id: I5c52d0cefb1a12597b26545014aa41527e99eb13 Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> --- M src/commonlib/bsd/include/commonlib/bsd/elog.h M util/cbfstool/eventlog.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/59578/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h index 29c781b..199694b 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/elog.h +++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h @@ -307,6 +307,7 @@ /* Chrome OS diagnostics-related events */ #define ELOG_TYPE_CROS_DIAGNOSTICS 0xb6 +#define ELOG_CROS_UPLOAD 0x00 #define ELOG_CROS_LAUNCH_DIAGNOSTICS 0x01 struct elog_event_extended_event { diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index 1fd4113..e873e82 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -535,6 +535,7 @@ }; static const struct valstr cros_diagnostics_types[] = { + {ELOG_CROS_UPLOAD, "Upload Metrics"}, {ELOG_CROS_LAUNCH_DIAGNOSTICS, "Launch Diagnostics"}, {0, NULL}, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c52d0cefb1a12597b26545014aa41527e99eb13 Gerrit-Change-Number: 59578 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: WIP: drivers/intel/retimer: Map correct physical port to EC port
by build bot (Jenkins) (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59577 ) Change subject: WIP: drivers/intel/retimer: Map correct physical port to EC port ...................................................................... Patch Set 1: (6 comments) File src/drivers/intel/usb4/retimer/retimer.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134112): https://review.coreboot.org/c/coreboot/+/59577/comment/93c58e8a_da7bc84c PS1, Line 349: for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134112): https://review.coreboot.org/c/coreboot/+/59577/comment/efd25f1a_7af3b037 PS1, Line 352: printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", i, ec_port); trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134112): https://review.coreboot.org/c/coreboot/+/59577/comment/0874af20_d1d5e3bf PS1, Line 352: printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", i, ec_port); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134112): https://review.coreboot.org/c/coreboot/+/59577/comment/8a3d73a7_6a05f62d PS1, Line 357: ec_port++; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134112): https://review.coreboot.org/c/coreboot/+/59577/comment/d49470f7_6a3d0add PS1, Line 357: ec_port++; please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134112): https://review.coreboot.org/c/coreboot/+/59577/comment/b03c2cc5_12b9ef2d PS1, Line 357: ec_port++; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f9cb544d60dbb3450bd5bcd22a85c193de212cc Gerrit-Change-Number: 59577 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 11:34:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: WIP: drivers/intel/retimer: Map correct physical port to EC port
by Maulik V Vaghela (Code Review) 23 Nov '21

23 Nov '21

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59577 ) Change subject: WIP: drivers/intel/retimer: Map correct physical port to EC port ...................................................................... WIP: drivers/intel/retimer: Map correct physical port to EC port Change-Id: I2f9cb544d60dbb3450bd5bcd22a85c193de212cc Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/drivers/intel/usb4/retimer/retimer.c 1 file changed, 30 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/59577/1 diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index e549525..34d1831 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -334,13 +334,39 @@ } } +static uint8_t map_physical_port_to_ec_port(uint8_t usb_port) +{ + struct device *dev = NULL; + uint8_t ec_port = 0; + + const struct device *tcss_port_arr[] = { + DEV_PTR(tcss_usb3_port1), + DEV_PTR(tcss_usb3_port2), + DEV_PTR(tcss_usb3_port3), + DEV_PTR(tcss_usb3_port4), + }; + + for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) + { + if (i == usb_port) { + printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", i, ec_port); + return ec_port; + } + + if (is_dev_enabled(tcss_port_arr[i])) + ec_port++; + } + + return 0xFF; +} + static void usb4_retimer_fill_ssdt(const struct device *dev) { struct drivers_intel_usb4_retimer_config *config = dev->chip_info; const struct device *usb_device; static char dfp[DEVICE_PATH_MAX]; struct acpi_pld pld; - uint8_t dfp_port, usb_port; + uint8_t dfp_port, usb_port, ec_port; usb4_retimer_scope = acpi_device_scope(dev); if (!usb4_retimer_scope || !config) @@ -364,6 +390,7 @@ usb_device = config->dfp[dfp_port].typec_port; usb_port = usb_device->path.usb.port_id; + ec_port = map_physical_port_to_ec_port(usb_port); /* DFPx */ snprintf(dfp, sizeof(dfp), "DFP%1d", usb_port); @@ -408,8 +435,8 @@ acpigen_pop_len(); /* Host Router */ acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, - dev_path(dev)); + printk(BIOS_INFO, "%s: %s at %s with %d\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev), ec_port); } static struct device_operations usb4_retimer_dev_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/59577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f9cb544d60dbb3450bd5bcd22a85c193de212cc Gerrit-Change-Number: 59577 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/prodrive/hermes: Update r04 front audio config
by Arthur Heymans (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Patrick Rudolph, Christian Walter, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59545 ) Change subject: mb/prodrive/hermes: Update r04 front audio config ...................................................................... Patch Set 1: -Code-Review (1 comment) File src/mainboard/prodrive/hermes/variants/r04/hda_verb.c: https://review.coreboot.org/c/coreboot/+/59545/comment/3910488d_be074438 PS1, Line 48: board_cfg-> drop this -- To view, visit https://review.coreboot.org/c/coreboot/+/59545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3760f0a25e964cf0eba99d180fd6f3e8488af868 Gerrit-Change-Number: 59545 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 23 Nov 2021 11:11:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/baseboard/brask: Add power limits functions
by Alan Huang (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Hou-hsun Lee, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58241 ) Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions ...................................................................... Patch Set 14: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58241/comment/27bb98dc_f2abc3ea PS7, Line 9: Set PL and PsysPL for Brask. > Where did you get the values from? Fixed File src/mainboard/google/brya/variants/baseboard/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/58241/comment/8885e769_5b5f7962 PS12, Line 20: bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries, > if you make this a static function then you don't need the prototype above. Fixed. https://review.coreboot.org/c/coreboot/+/58241/comment/06cb94f7_99daba74 PS12, Line 121: > nit: extra blank line Fixed. File src/mainboard/google/brya/variants/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/58241/comment/e919d967_b279efe5 PS7, Line 20: /* Psys_pmax considerations. : * > Please use the recommented multi-line comment styles [1]. […] Done File src/mainboard/google/brya/variants/brask/ramstage.c: PS12: > Adding this file should be a separate change on top of the rest Separate to here https://review.coreboot.org/c/coreboot/+/59576 https://review.coreboot.org/c/coreboot/+/58241/comment/460e5845_30ebed81 PS12, Line 21: * > nit: space after `)` Fixed. https://review.coreboot.org/c/coreboot/+/58241/comment/efd62da5_42940bc3 PS12, Line 23: { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135, 135 }, > The psys_pmax_power should be same (257W) for all SKUs. […] Updated to 257. Yes, we didn't use it. Should I use these values somewhere? https://review.coreboot.org/c/coreboot/+/58241/comment/67e4f53c_8124cf87 PS12, Line 41: barral > `barrel` Fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 14 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 23 Nov 2021 11:01:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/primus: Update thermal table for primus
by Ariel Fang (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Tim Wawrzynczak. Ariel Fang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59182 ) Change subject: mb/google/brya/var/primus: Update thermal table for primus ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d Gerrit-Change-Number: 59182 Gerrit-PatchSet: 8 Gerrit-Owner: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 10:54:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/google/chromeec: Add powerinfo support
by Sumeet R Pawnikar (Code Review) 23 Nov '21

23 Nov '21

Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59189 to look at the new patch set (#3). Change subject: ec/google/chromeec: Add powerinfo support ...................................................................... ec/google/chromeec: Add powerinfo support Add powerinfo support to get the system power source details. BUG=b:205928013 BUG=None TEST=Build and test powerinfo parameters on byra Change-Id: I75b109592b327df11d1101bcf32a364c2ae7feac Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h 3 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/59189/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75b109592b327df11d1101bcf32a364c2ae7feac Gerrit-Change-Number: 59189 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/var/brask: Set PL and PsysPL
by Alan Huang (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Tim Wawrzynczak. Alan Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59576 ) Change subject: mb/google/brya/var/brask: Set PL and PsysPL ...................................................................... mb/google/brya/var/brask: Set PL and PsysPL Set the defalut PL1, PL2 and PL4 according to Intel's spec. Set PsysPL2 and PsysPmax according to Brask's spec. BUG=b:193864533 BRANCH=none TEST=Compare the measured power from adapter with the value of 'psys' from the command 'dump_intel_rapl_consumption'. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 --- M src/mainboard/google/brya/variants/brask/Makefile.inc A src/mainboard/google/brya/variants/brask/ramstage.c 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59576/1 diff --git a/src/mainboard/google/brya/variants/brask/Makefile.inc b/src/mainboard/google/brya/variants/brask/Makefile.inc index d38141c..bc39984 100644 --- a/src/mainboard/google/brya/variants/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/brask/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/brask/ramstage.c b/src/mainboard/google/brya/variants/brask/ramstage.c new file mode 100644 index 0000000..73b1d7b --- /dev/null +++ b/src/mainboard/google/brya/variants/brask/ramstage.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 5000, 45000, 80000, 80000, 159000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts), psys_pmax (Watts) */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135, 257 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135, 257 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230, 257 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230, 257 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230, 257 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230, 257 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in brask, the serial shunt resistor is 0.005ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 13.52A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v = (0.005ohm x 13.52A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.47 = 15K / (15K + 16.9K) + * Since there is no voltage information from PSYS, different voltage input + * would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax sholud be 15v x 13.52A = 202.8W + * For Type-C 20V, the Psys_pmax should be 20v x 13.52A = 270.4W + * For a barrel jack, the Psys_pmax should be 19.5v x 13.52A = 263.6W + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 13520, + .bj_volts_mv = 19500 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Gerrit-Change-Number: 59576 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021