coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/variants/primus: update gpios for power consumption
by build bot (Jenkins) (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59563 ) Change subject: mb/google/brya/variants/primus: update gpios for power consumption ...................................................................... Patch Set 1: (3 comments) File src/mainboard/google/brya/variants/primus/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134088): https://review.coreboot.org/c/coreboot/+/59563/comment/3fc97912_b44a4268 PS1, Line 48: int sku = gpio_get(GPP_T2); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134088): https://review.coreboot.org/c/coreboot/+/59563/comment/39fdd958_5044bf78 PS1, Line 50: if ( sku == 1 ) space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134088): https://review.coreboot.org/c/coreboot/+/59563/comment/66744838_25ee54f9 PS1, Line 50: if ( sku == 1 ) space prohibited before that close parenthesis ')' -- To view, visit https://review.coreboot.org/c/coreboot/+/59563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148 Gerrit-Change-Number: 59563 Gerrit-PatchSet: 1 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 07:20:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: update gpios for power consumption
by Malik Hsu (Code Review) 23 Nov '21

23 Nov '21

Malik Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59563 ) Change subject: mb/google/brya/variants/primus: update gpios for power consumption ...................................................................... mb/google/brya/variants/primus: update gpios for power consumption In different sku, some unused GPIO pins are processed by NC for power consumption. BUG=b:196790249 TEST=emerge-brya coreboot chromeos-bootimage and check power Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com> Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148 --- M src/mainboard/google/brya/variants/primus/variant.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/59563/1 diff --git a/src/mainboard/google/brya/variants/primus/variant.c b/src/mainboard/google/brya/variants/primus/variant.c index e10648d..e17dbb6 100644 --- a/src/mainboard/google/brya/variants/primus/variant.c +++ b/src/mainboard/google/brya/variants/primus/variant.c @@ -5,6 +5,8 @@ #include <device/device.h> #include <drivers/i2c/hid/chip.h> #include <fw_config.h> +#include <gpio.h> +#include <soc/gpio.h> static void devtree_update_emmc_rtd3(uint32_t board_ver) { @@ -27,6 +29,30 @@ config->hid = "RTL5682"; } +static const struct pad_config nvme_disable_pads[] = { + PAD_NC(GPP_B2, NONE), /* B2 : VRALERT# ==> M2_SSD_PLA_L */ + PAD_NC(GPP_B4, NONE), /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_NC(GPP_D3, NONE), /* D3 : ISH_GP3 ==> M2_SSD_PLN_L */ + PAD_NC(GPP_D5, NONE), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_NC(GPP_D11, NONE), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ +}; + +static const struct pad_config emmc_disable_pads[] = { + PAD_NC(GPP_B3, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ + PAD_NC(GPP_E20, NONE), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_NC(GPP_F19, NONE), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ +}; + +static void get_sku_and_set_gpio(void) +{ + int sku = gpio_get(GPP_T2); + + if ( sku == 1 ) + gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); + else + gpio_configure_pads(emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads)); +} + void variant_devtree_update(void) { uint32_t board_ver = board_id(); -- To view, visit https://review.coreboot.org/c/coreboot/+/59563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148 Gerrit-Change-Number: 59563 Gerrit-PatchSet: 1 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/delbin: Add fw_config probe for ALC5682-VD & VS
by Frank Chu (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Anson Tseng, Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59557 ) Change subject: mb/google/volteer/var/delbin: Add fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: sorry, Could you help review, why below error message => src/mainboard/google/volteer/variants/delbin/variant.c has no recognized SPDX identifier. -- To view, visit https://review.coreboot.org/c/coreboot/+/59557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieef638f78edd3428e572a76f06fb9c8757278971 Gerrit-Change-Number: 59557 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Anson Tseng <ansontseng(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 23 Nov 2021 07:19:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Subrata Banik (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Ravindra, Sridhar Siricilla, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... Patch Set 12: (3 comments) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/55364/comment/cc0ca5d8_56456ba0 PS12, Line 145: cse_fw_sync() must be called after DRAM initialization as : * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) : * is expected to be executed after DRAM initialization. what happen to this recommendation. This comment looks like an advisory which we don't care now ? Any reason for this ? if yes, can we highlight the same in commit msg as well https://review.coreboot.org/c/coreboot/+/55364/comment/968f19fe_88edc0fd PS12, Line 140: can we add a timestamp around this to know how much time we are really spending for this command if possible ? https://review.coreboot.org/c/coreboot/+/55364/comment/2a728c78_bb6658c8 PS12, Line 142: cse_fw_sync can you move this call immediately after heci_init() ? -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 23 Nov 2021 07:13:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value
by Kane Chen (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Kane Chen, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59562 to look at the new patch set (#4). Change subject: soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value ...................................................................... soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value On ADL, we actually use debug consent 2 for soc debug by DBC Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59562/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 Gerrit-Change-Number: 59562 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value
by Kane Chen (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Kane Chen, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59562 to look at the new patch set (#3). Change subject: soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value ...................................................................... soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value On ADL, we actually use debug consent 2 for soc debug by DBC Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59562/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 Gerrit-Change-Number: 59562 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value
by Kane Chen (Code Review) 23 Nov '21

23 Nov '21

Attention is currently required from: Kane Chen, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59562 to look at the new patch set (#2). Change subject: soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value ...................................................................... soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value On ADL, we actually use debug consent 2 for soc debug by DBC Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59562/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 Gerrit-Change-Number: 59562 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default...
by Kane Chen (Code Review) 23 Nov '21

23 Nov '21

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59562 ) Change subject: soc/intel/alderlake: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value ...................................................................... soc/intel/alderlake: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value On ADL, we actually use debug consent 2 for soc debug by DBC Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59562/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 58b9051..959ce9c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -288,7 +288,7 @@ int "Debug Consent for ADL" # USB DBC is more common for developers so make this default to 3 if # SOC_INTEL_DEBUG_CONSENT=y - default 3 if SOC_INTEL_DEBUG_CONSENT + default 2 if SOC_INTEL_DEBUG_CONSENT default 0 help This is to control debug interface on SOC. @@ -296,9 +296,8 @@ PlatformDebugConsent in FspmUpd.h has the details. Desired platform debug type are - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), - 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), - 6:Enable (2-wire DCI OOB), 7:Manual + 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), + 7:Manual config DATA_BUS_WIDTH int -- To view, visit https://review.coreboot.org/c/coreboot/+/59562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 Gerrit-Change-Number: 59562 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/kano: swap TPM i2c with touchscreen i2c for EVT
by David Wu (Code Review) 23 Nov '21

23 Nov '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59560 ) Change subject: mb/google/brya/var/kano: swap TPM i2c with touchscreen i2c for EVT ...................................................................... mb/google/brya/var/kano: swap TPM i2c with touchscreen i2c for EVT Kano EVT will exchange i2c port for touchscreen and cr50. BUG=b:195853169 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/kano/overridetree.cb 3 files changed, 48 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/59560/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1b4f6ae..6e61698 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -72,7 +72,15 @@ config DRIVER_TPM_I2C_BUS hex - default 0x3 + default 0x3 if BOARD_GOOGLE_BRYA0 + default 0x3 if BOARD_GOOGLE_BRASK + default 0x3 if BOARD_GOOGLE_PRIMUS + default 0x3 if BOARD_GOOGLE_GIMBLE + default 0x3 if BOARD_GOOGLE_REDRIX + default 0x1 if BOARD_GOOGLE_KANO + default 0x3 if BOARD_GOOGLE_TAEKO + default 0x3 if BOARD_GOOGLE_FELWINTER + default 0x3 if BOARD_GOOGLE_ANAHERA config DRIVER_TPM_I2C_ADDR hex diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 818ddd0..d77abea 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -108,10 +108,6 @@ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -133,6 +129,10 @@ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index d7ae3da..ca98096 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -216,37 +216,10 @@ end end #I2C0 device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN90FC"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" - register "generic.reset_off_delay_ms" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "6" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end - end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - # GPP_D6 is the IRQ source, and GPP_D17 is the wake source - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)" - register "key.wake_gpe" = "GPE0_DW1_17" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end end end device ref i2c2 on @@ -405,10 +378,37 @@ end end device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_D6 is the IRQ source, and GPP_D17 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)" + register "key.wake_gpe" = "GPE0_DW1_17" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end end end device ref i2c5 on -- To view, visit https://review.coreboot.org/c/coreboot/+/59560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465 Gerrit-Change-Number: 59560 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Update SA & IGD DIDs Table Update SA table as ...
by Rick Lee (Code Review) 23 Nov '21

23 Nov '21

Rick Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59559 ) Change subject: soc/intel/elkhartlake: Update SA & IGD DIDs Table Update SA table as per latest EDS (Doc no: 601458). Add extra SKUs accordingly. ...................................................................... soc/intel/elkhartlake: Update SA & IGD DIDs Table Update SA table as per latest EDS (Doc no: 601458). Add extra SKUs accordingly. Signed-off-by: Rick Lee <rick.lee(a)intel.com> Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/elkhartlake/bootblock/report_platform.c 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/59559/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c6ef121..8d9c300 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3963,6 +3963,8 @@ #define PCI_DEVICE_ID_INTEL_EHL_ID_11 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_12 0x4518 #define PCI_DEVICE_ID_INTEL_EHL_ID_13 0x451A +#define PCI_DEVICE_ID_INTEL_EHL_ID_14 0x4536 +#define PCI_DEVICE_ID_INTEL_EHL_ID_15 0x451C #define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22 #define PCI_DEVICE_ID_INTEL_JSL_ID_2 0x4e26 #define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 45e1d42..572b417 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -403,6 +403,8 @@ PCI_DEVICE_ID_INTEL_EHL_ID_11, PCI_DEVICE_ID_INTEL_EHL_ID_12, PCI_DEVICE_ID_INTEL_EHL_ID_13, + PCI_DEVICE_ID_INTEL_EHL_ID_14, + PCI_DEVICE_ID_INTEL_EHL_ID_15, PCI_DEVICE_ID_INTEL_JSL_ID_1, PCI_DEVICE_ID_INTEL_JSL_ID_2, PCI_DEVICE_ID_INTEL_JSL_ID_3, diff --git a/src/soc/intel/elkhartlake/bootblock/report_platform.c b/src/soc/intel/elkhartlake/bootblock/report_platform.c index 8d93e4d..9cb32cc 100644 --- a/src/soc/intel/elkhartlake/bootblock/report_platform.c +++ b/src/soc/intel/elkhartlake/bootblock/report_platform.c @@ -42,6 +42,8 @@ { PCI_DEVICE_ID_INTEL_EHL_ID_11, "Elkhartlake SKU-11" }, { PCI_DEVICE_ID_INTEL_EHL_ID_12, "Elkhartlake SKU-12" }, { PCI_DEVICE_ID_INTEL_EHL_ID_13, "Elkhartlake SKU-13" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_14, "Elkhartlake SKU-14" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_15, "Elkhartlake SKU-15" }, }; static struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/59559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706 Gerrit-Change-Number: 59559 Gerrit-PatchSet: 1 Gerrit-Owner: Rick Lee <rick.lee(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021