coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/kano: Update thermal table
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59572 ) Change subject: mb/google/brya/var/kano: Update thermal table ...................................................................... mb/google/brya/var/kano: Update thermal table Update thermal setting from thermal team. BUG=b:205648035 TEST=build and verified by thermal team. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: If5082462b79c88ecf510f7a552381c792604366e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59572 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 27 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index d7ae3da..56dfc6f 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -59,23 +59,39 @@ .target = DPTF_CPU, .thresholds = { TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), + TEMP_PCT(75, 80), + TEMP_PCT(68, 70), + TEMP_PCT(62, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(40, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(60, 90), + TEMP_PCT(55, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40), + TEMP_PCT(36, 30), } } }" ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), - [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), @@ -83,15 +99,15 @@ register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, - .max_power = 15000, + .min_power = 18000, + .max_power = 28000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { - .min_power = 55000, - .max_power = 55000, + .min_power = 40000, + .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, -- To view, visit https://review.coreboot.org/c/coreboot/+/59572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5082462b79c88ecf510f7a552381c792604366e Gerrit-Change-Number: 59572 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: move bustracker_init before watchdog reset again
by Rex-BC Chen (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has removed Xi Chen from this change. ( https://review.coreboot.org/c/coreboot/+/59667 ) Change subject: soc/mediatek: move bustracker_init before watchdog reset again ...................................................................... Removed reviewer Xi Chen. -- To view, visit https://review.coreboot.org/c/coreboot/+/59667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Gerrit-Change-Number: 59667 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59546 ) Change subject: arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax ...................................................................... arch/{arm,arm64,ppc64,riscv}: Add noop cpu_relax The cpu_relax method is defined for x86. This CL adds a no-op method so that it can be used in common code. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ifcb4546ceb2894eeb37589d0282b7e076d7a4747 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59546 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm/include/armv4/arch/cpu.h M src/arch/arm/include/armv7/arch/cpu.h M src/arch/arm64/include/armv8/arch/cpu.h M src/arch/ppc64/include/arch/cpu.h M src/arch/riscv/include/arch/cpu.h 5 files changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/arch/arm/include/armv4/arch/cpu.h b/src/arch/arm/include/armv4/arch/cpu.h index 8a1b00e..4c6cdf8 100644 --- a/src/arch/arm/include/armv4/arch/cpu.h +++ b/src/arch/arm/include/armv4/arch/cpu.h @@ -3,6 +3,8 @@ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ +static inline void cpu_relax(void) { } + #define asmlinkage #endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 3f1f1ae..e3154e9 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -6,6 +6,8 @@ #include <stdint.h> #include <device/device.h> +static inline void cpu_relax(void) { } + #define asmlinkage struct cpu_driver { diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 15b2065..e5e8a7c 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -3,6 +3,9 @@ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ +/* TODO: Implement using SEV/WFE if this is ever actually used. */ +static inline void cpu_relax(void) { } + #define asmlinkage struct cpu_driver { }; diff --git a/src/arch/ppc64/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h index 5e5ba30..638406d 100644 --- a/src/arch/ppc64/include/arch/cpu.h +++ b/src/arch/ppc64/include/arch/cpu.h @@ -5,6 +5,8 @@ #include <device/device.h> +static inline void cpu_relax(void) { } + #define asmlinkage struct cpu_driver { diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 7cf9461..d51d8a9 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -6,6 +6,8 @@ #include <arch/encoding.h> #include <device/device.h> +static inline void cpu_relax(void) { } + #define asmlinkage struct cpu_driver { -- To view, visit https://review.coreboot.org/c/coreboot/+/59546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcb4546ceb2894eeb37589d0282b7e076d7a4747 Gerrit-Change-Number: 59546 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: move bustracker_init before watchdog reset again
by Rex-BC Chen (Code Review) 25 Nov '21

25 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59667 ) Change subject: soc/mediatek: move bustracker_init before watchdog reset again ...................................................................... soc/mediatek: move bustracker_init before watchdog reset again The checking register will be cleared after resetting, so we move bustracker dump before resetting again. TEST=bustracker shows status before wdt reset BUG=b:207450135 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/bootblock.c M src/soc/mediatek/mt8195/soc.c 6 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59667/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index a75ac28..b04acb5 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -10,6 +10,7 @@ bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c +bootblock-y += ../common/tracker.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c @@ -63,7 +64,6 @@ ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c -ramstage-y += ../common/tracker.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 17fd27e..3adf5c1 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -4,11 +4,13 @@ #include <soc/eint_event.h> #include <soc/mmu_operations.h> #include <soc/pll.h> +#include <soc/tracker_common.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); + bustracker_init(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 355827a..006a212 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -9,7 +9,6 @@ #include <soc/mcupm.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> -#include <soc/tracker_common.h> #include <soc/ufs.h> #include <symbols.h> @@ -34,7 +33,6 @@ if (CONFIG(MTK_DFD)) dfd_init(); ufs_disable_refclk(); - bustracker_init(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index c6f4226..a7ada28 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/tracker.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c @@ -50,7 +51,7 @@ romstage-y += mt6691.c romstage-y += mt6360.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c -ramstage-y += ../common/tracker.c + ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c diff --git a/src/soc/mediatek/mt8195/bootblock.c b/src/soc/mediatek/mt8195/bootblock.c index 17fd27e..3adf5c1 100644 --- a/src/soc/mediatek/mt8195/bootblock.c +++ b/src/soc/mediatek/mt8195/bootblock.c @@ -4,11 +4,13 @@ #include <soc/eint_event.h> #include <soc/mmu_operations.h> #include <soc/pll.h> +#include <soc/tracker_common.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); + bustracker_init(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 80ca3d9..d28f668 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -10,7 +10,6 @@ #include <soc/mcupm.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> -#include <soc/tracker_common.h> #include <soc/ufs.h> #include <symbols.h> @@ -38,7 +37,6 @@ ufs_disable_refclk(); hdmi_low_power_setting(); - bustracker_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/59667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Gerrit-Change-Number: 59667 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Allow to set TXT BIOS Data Region version
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59513 ) Change subject: security/intel/txt: Allow to set TXT BIOS Data Region version ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2550bd4008559bd47de9e35f8b1c7b52e6e0f5f Gerrit-Change-Number: 59513 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:42:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Add support for DPR
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59512 ) Change subject: nb/intel/sandybridge: Add support for DPR ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: > Where is it set? In a follow-up. -- To view, visit https://review.coreboot.org/c/coreboot/+/59512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 Gerrit-Change-Number: 59512 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:41:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/graphics/Kconfig: Guard options
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59471 ) Change subject: soc/intel/graphics/Kconfig: Guard options ...................................................................... soc/intel/graphics/Kconfig: Guard options Change-Id: I3c252e31867e4560fb5aaf12273288f4ff18ae3d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59471 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/graphics/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index 8288150..1ec074e 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -3,6 +3,8 @@ help Intel Processor common Graphics support +if SOC_INTEL_COMMON_BLOCK_GRAPHICS + config SOC_INTEL_CONFIGURE_DDI_A_4_LANES bool help @@ -16,3 +18,5 @@ Selected by mainboard user that need to skip IGD initialization where OS can only use one GPU hence need to disable IGD and don't need to run FSP GOP. + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c252e31867e4560fb5aaf12273288f4ff18ae3d Gerrit-Change-Number: 59471 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kano: set power limits for thermal
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59091 ) Change subject: mb/google/brya/var/kano: set power limits for thermal ...................................................................... mb/google/brya/var/kano: set power limits for thermal Set power limits for kano based on CPU SKUs. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59091 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kano/Makefile.inc A src/mainboard/google/brya/variants/kano/ramstage.c 2 files changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, but someone else must approve YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/Makefile.inc b/src/mainboard/google/brya/variants/kano/Makefile.inc index 9ea19de..66dcf7e 100644 --- a/src/mainboard/google/brya/variants/kano/Makefile.inc +++ b/src/mainboard/google/brya/variants/kano/Makefile.inc @@ -6,3 +6,4 @@ ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kano/ramstage.c b/src/mainboard/google/brya/variants/kano/ramstage.c new file mode 100644 index 0000000..9b26cbb --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 18000, 28000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 18000, 28000, 40000, 40000, 105000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19 Gerrit-Change-Number: 59091 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: David Wu, Rory Liu, Zhuohao Lee, Alan Huang. Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59086 to look at the new patch set (#9). Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... drivers/net/r8168: Add support for Realtek RT8125 The Realtek RT8168 and RT8125 have a similar programming interface, therefore add the PCI device ID for the RT8125 into driver for support. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage. Test along with CL:59087 on brask whose NIC is RT8125. Check if the default MAC is written into the NIC. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 --- M src/drivers/net/r8168.c M src/include/device/pci_ids.h 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 9 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by build bot (Jenkins) (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... Patch Set 3: Verified-1 (5 comments) File src/soc/intel/alderlake/retimer.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134329): https://review.coreboot.org/c/coreboot/+/59666/comment/a851960c_24c72246 PS3, Line 20: for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134329): https://review.coreboot.org/c/coreboot/+/59666/comment/2ec8ea88_73511f29 PS3, Line 28: ec_port++; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134329): https://review.coreboot.org/c/coreboot/+/59666/comment/73d3f4ea_a89c4b4a PS3, Line 28: ec_port++; please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134329): https://review.coreboot.org/c/coreboot/+/59666/comment/9fab7544_18d42ddc PS3, Line 28: ec_port++; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134329): https://review.coreboot.org/c/coreboot/+/59666/comment/5b02e7a2_babf5fa2 PS3, Line 32: die("Couldn't find correct port mapping or Invalid input port \n"); unnecessary whitespace before a quoted newline -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:23:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021