coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by build bot (Jenkins) (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... Patch Set 2: (5 comments) File src/soc/intel/alderlake/retimer.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134328): https://review.coreboot.org/c/coreboot/+/59666/comment/d6180e1f_1ec070a7 PS2, Line 20: for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134328): https://review.coreboot.org/c/coreboot/+/59666/comment/615eae76_7c5eb7ce PS2, Line 28: ec_port++; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134328): https://review.coreboot.org/c/coreboot/+/59666/comment/e31f8e4d_2334aeee PS2, Line 28: ec_port++; please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134328): https://review.coreboot.org/c/coreboot/+/59666/comment/53afff05_0ac04184 PS2, Line 28: ec_port++; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134328): https://review.coreboot.org/c/coreboot/+/59666/comment/820cc63c_0c2af1ea PS2, Line 32: die("Couldn't find correct port mapping or Invalid input port \n"); unnecessary whitespace before a quoted newline -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:12:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by build bot (Jenkins) (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... Patch Set 1: (7 comments) File src/soc/intel/alderlake/retimer.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134327): https://review.coreboot.org/c/coreboot/+/59666/comment/01248599_6f4d12af PS1, Line 20: for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134327): https://review.coreboot.org/c/coreboot/+/59666/comment/b8a8baeb_4f84962a PS1, Line 23: printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", i, ec_port); trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134327): https://review.coreboot.org/c/coreboot/+/59666/comment/8e871d51_d63a75c7 PS1, Line 23: printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", i, ec_port); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134327): https://review.coreboot.org/c/coreboot/+/59666/comment/9b469054_c66ccff2 PS1, Line 28: ec_port++; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134327): https://review.coreboot.org/c/coreboot/+/59666/comment/1c1e9125_d618691a PS1, Line 28: ec_port++; please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134327): https://review.coreboot.org/c/coreboot/+/59666/comment/cf0ccd95_e73e991d PS1, Line 28: ec_port++; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134327): https://review.coreboot.org/c/coreboot/+/59666/comment/521a7af9_3c218723 PS1, Line 32: die("Couldn't find correct port mapping or Invalid input port \n"); unnecessary whitespace before a quoted newline -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:09:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/usb4/retimer: Add function to correct EC port mapping
by Maulik V Vaghela (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59665 to look at the new patch set (#2). Change subject: drivers/intel/usb4/retimer: Add function to correct EC port mapping ...................................................................... drivers/intel/usb4/retimer: Add function to correct EC port mapping Currently coreboot interprets TCSS port number as per physical port number while EC abstracts port number and provides indices as port number. For example, if TCSS port 1 and 3 are enabled on the board, coreboot will interpret port numbers as 0 and 2, but since only 2 ports are enabled in the system EC will assign port numbers as 0 and 1. This creates a port number mismatch while communicating between EC and coreboot. This patch addresses issue where SoC can implement function to map correct EC port as per port enabled in mainboard. BUG=b:207057940 BRANCH=None TEST=Check if code compiles successfully. Functionality will work once function is implemented in SoC code. Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/intel/usb4/retimer/retimer.h 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/59665/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Gerrit-Change-Number: 59665 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by Maulik V Vaghela (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... soc/intel/alderlake: Implement function to map physical port to EC port Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. To correct this, coreboot has implemented function which converts coreboot physical port mapping to EC's abstract port mapping. Each SoC needs to implement this weak function since only SoC will have correct physical port mapping data. This function should resolve issue of port mismatch since coreboot will count only enabled ports and provide correct EC port number in return. BUG=b:207057940 BRANCH=None TEST=Check if retimer update works on Redrix and correct port information is passed to EC. Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/retimer.c 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59666/1 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index a11352f..7c7018a 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c +ramstage-y += retimer.c ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += vr_config.c diff --git a/src/soc/intel/alderlake/retimer.c b/src/soc/intel/alderlake/retimer.c new file mode 100644 index 0000000..d0b2a8e --- /dev/null +++ b/src/soc/intel/alderlake/retimer.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <drivers/intel/usb4/retimer/retimer.h> +#include <intelblocks/tcss.h> +#include <string.h> +#include "retimer.h" + +uint8_t map_physical_port_to_ec_port(uint8_t usb_port) +{ + uint8_t ec_port = 0; + + const struct device *tcss_port_arr[] = { + DEV_PTR(tcss_usb3_port1), + DEV_PTR(tcss_usb3_port2), + DEV_PTR(tcss_usb3_port3), + DEV_PTR(tcss_usb3_port4), + }; + + for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) + { + if (i == usb_port) { + printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", i, ec_port); + return ec_port; + } + + if (is_dev_enabled(tcss_port_arr[i])) + ec_port++; + } + + // Code should not come here if usb_port input is correct + die("Couldn't find correct port mapping or Invalid input port \n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/usb4/retimer: Add function to correct EC port mapping
by Maulik V Vaghela (Code Review) 25 Nov '21

25 Nov '21

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59665 ) Change subject: drivers/intel/usb4/retimer: Add function to correct EC port mapping ...................................................................... drivers/intel/usb4/retimer: Add function to correct EC port mapping Currently coreboot interprets TCSS port number as per physical port number while EC abstracts port number and provides indices as port number. For example, if TCSS port 1 and 3 are enabled on the board, coreboot will interpret port number as 0 and 2, but since only 2 ports are enabled in the system EC will assign port number as 0 and 1. This creates a port number mismatch while communicating between EC and coreboot. This patch addresses issue where SoC can implement function to map correct EC port as per port enabled in mainboard. BUG=b:207057940 BRANCH=None TEST=Check if code compiles successfully. Functionality will work once function is implemented in SoC code. Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/intel/usb4/retimer/retimer.h 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/59665/1 diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index e549525..788df9e 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -396,7 +396,7 @@ /* Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); acpigen_pop_len(); - usb4_retimer_write_dsm(usb_port, INTEL_USB4_RETIMER_DSM_UUID, + usb4_retimer_write_dsm(ec_port, INTEL_USB4_RETIMER_DSM_UUID, usb4_retimer_callbacks, ARRAY_SIZE(usb4_retimer_callbacks), (void *)&config->dfp[dfp_port].power_gpio); /* Default case: Return (Buffer (One) { 0x0 }) */ @@ -436,3 +436,18 @@ __weak void ec_retimer_fw_update(uint8_t data) { } + +/* + * This function will convert CPU physical port mapping to abstract + * EC port mapping. For example, board might have enabled TCSS port 1 + * and 3 as per physical port mapping. Since only 2 TCSS ports are enabled + * EC will name it as port 0 and port 1. So there will be mismatch when + * coreboot sends index for port 3. + * Each SoC code using retimer driver needs to implement this function + * since SoC will have physical port details. + */ +__weak uint8_t map_physical_port_to_ec_port(uint8_t usb_port) +{ + // By default assume that physical port index = Ec port index. + return usb_port; +} diff --git a/src/drivers/intel/usb4/retimer/retimer.h b/src/drivers/intel/usb4/retimer/retimer.h index 5a040a0..3f136dd 100644 --- a/src/drivers/intel/usb4/retimer/retimer.h +++ b/src/drivers/intel/usb4/retimer/retimer.h @@ -30,5 +30,15 @@ const char *ec_retimer_fw_update_path(void); void ec_retimer_fw_update(uint8_t data); +/* + * This function will convert CPU physical port mapping to abstract + * EC port mapping. For example, board might have enabled TCSS port 1 + * and 3 as per physical port mapping. Since only 2 TCSS ports are enabled + * EC will name it as port 0 and port 1. So there will be mismatch when + * coreboot sends index for port 3. + * Each SoC code using retimer driver needs to implement this function + * since SoC will have physical port details. + */ +uint8_t map_physical_port_to_ec_port(uint8_t usb_port); #endif /* _DRIVERS_INTEL_USB4_RETIMER_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Gerrit-Change-Number: 59665 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool/Makefile: Fix building as standalone tool
by Patrick Georgi (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Maciej Pijanowski, Stefan Reinauer, Angel Pons, Julius Werner, Arthur Heymans, Krystian Hebel. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59663 ) Change subject: util/ifdtool/Makefile: Fix building as standalone tool ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: We should deduplicate that stuff so that Makefile reuses Makefile.inc, but it gets the job done for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/59663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2bbc07ddd87d885e2d6f5c7f2bd501e5c4e3b0 Gerrit-Change-Number: 59663 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 09:32:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/testing: Add ifdtool to tools to be tested
by Patrick Georgi (Code Review) 25 Nov '21

25 Nov '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59664 ) Change subject: util/testing: Add ifdtool to tools to be tested ...................................................................... util/testing: Add ifdtool to tools to be tested Ensure that the separate Makefile doesn't break. Change-Id: I0fbe37dc01e46022c5e6de5629eb99f6b86b0b14 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/testing/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/59664/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 0b93425..1411c7e 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -54,6 +54,7 @@ cbmem \ ectool \ futility \ +ifdtool \ intelmetool \ inteltool \ intelvbttool \ -- To view, visit https://review.coreboot.org/c/coreboot/+/59664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fbe37dc01e46022c5e6de5629eb99f6b86b0b14 Gerrit-Change-Number: 59664 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55039 ) Change subject: util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: This broke building ifdtool as a standalone tool. CB:59663 fixes it. -- To view, visit https://review.coreboot.org/c/coreboot/+/55039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia88c0625cefa1e594ac1849271a71c3aacc8ce78 Gerrit-Change-Number: 55039 Gerrit-PatchSet: 10 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 09:16:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool/Makefile: Fix building as standalone tool
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59663 ) Change subject: util/ifdtool/Makefile: Fix building as standalone tool ...................................................................... util/ifdtool/Makefile: Fix building as standalone tool Commit f1e401c6cb70 (util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE) makes use of endianness conversion macros in cbfstool's FMAP code, which is also used by ifdtool. At least on Linux, the <endian.h> header provides these helpers, but only when `__USE_MISC` is defined, which is defined in the <ctypes.h> header when `_DEFAULT_SOURCE` is defined. This was accounted for in `Makefile.inc`, but not in `Makefile`. As a result, trying to build ifdtool as a standalone tool (i.e. not as part of building a coreboot image) results in build errors because the endianness conversion macros are not defined. Define `_DEFAULT_SOURCE` in `Makefile` to fix the build errors. Change-Id: I8c2bbc07ddd87d885e2d6f5c7f2bd501e5c4e3b0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/ifdtool/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/59663/1 diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index e8d818c..473dc08 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -11,6 +11,7 @@ CFLAGS += -I../../src/commonlib/include -I../../src/commonlib/bsd/include CFLAGS += -I../cbfstool/flashmap CFLAGS += -include ../../src/commonlib/bsd/include/commonlib/bsd/compiler.h +CFLAGS += -D_DEFAULT_SOURCE # for endianness converting functions LDFLAGS = OBJS = ifdtool.o -- To view, visit https://review.coreboot.org/c/coreboot/+/59663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2bbc07ddd87d885e2d6f5c7f2bd501e5c4e3b0 Gerrit-Change-Number: 59663 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: oprom/realmode/x86.c: Fix building for ENV_X86_64
by build bot (Jenkins) (Code Review) 25 Nov '21

25 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59660 ) Change subject: oprom/realmode/x86.c: Fix building for ENV_X86_64 ...................................................................... Patch Set 2: (2 comments) File src/device/oprom/realmode/x86.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134321): https://review.coreboot.org/c/coreboot/+/59660/comment/4f5bfd8b_db7f2d8b PS2, Line 94: .rip=X86_EIP, spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134321): https://review.coreboot.org/c/coreboot/+/59660/comment/520042ff_24018a1d PS2, Line 100: .rflags=X86_EFLAGS spaces required around that '=' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/59660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ce8d56da326aeff5ff9b400ded02d4309372519 Gerrit-Change-Number: 59660 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 08:56:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021