coreboot-gerrit November 2021

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Change in coreboot[master]: security/intel/txt: Implement GETSEC PARAMETER dumping
by Arthur Heymans (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59516 ) Change subject: security/intel/txt: Implement GETSEC PARAMETER dumping ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b2c8337a8d86000a5b43788840d15146b662598 Gerrit-Change-Number: 59516 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 07:44:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Remove unused region device
by Arthur Heymans (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59515 ) Change subject: security/intel/txt: Remove unused region device ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98afba35403d5d2cd9eeb7df6d1ca0171894e9d4 Gerrit-Change-Number: 59515 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 07:44:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Correct reporting of chipset production fuse state
by Arthur Heymans (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59514 ) Change subject: security/intel/txt: Correct reporting of chipset production fuse state ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86c5a9e1d162630a1cf61435d1014edabf104b0 Gerrit-Change-Number: 59514 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 07:43:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Allow to set TXT BIOS Data Region version
by Arthur Heymans (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Paul Menzel, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59513 ) Change subject: security/intel/txt: Allow to set TXT BIOS Data Region version ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2550bd4008559bd47de9e35f8b1c7b52e6e0f5f Gerrit-Change-Number: 59513 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 07:42:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Add support for DPR
by Arthur Heymans (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59512 ) Change subject: nb/intel/sandybridge: Add support for DPR ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Where is it set? -- To view, visit https://review.coreboot.org/c/coreboot/+/59512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 Gerrit-Change-Number: 59512 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 07:41:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth
by David Wu (Code Review) 25 Nov '21

25 Nov '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59658 ) Change subject: mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth ...................................................................... mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth BlueTooth disappeared after disabled USB2 port 9, so we need to re-enable it. BUG=none TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I7971509d7428562c80e781339ead059a189cea13 --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/59658/1 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index d7ae3da..54a7d39 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -20,7 +20,6 @@ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable M.2 Bluetooth register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN -- To view, visit https://review.coreboot.org/c/coreboot/+/59658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7971509d7428562c80e781339ead059a189cea13 Gerrit-Change-Number: 59658 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/medaitek/mt8186: fix wrong condition of RTC drivers
by Rex-BC Chen (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59653 to look at the new patch set (#2). Change subject: soc/medaitek/mt8186: fix wrong condition of RTC drivers ...................................................................... soc/medaitek/mt8186: fix wrong condition of RTC drivers We need to report error while rtc_xosc_write() returns false. TEST=error logs for RTC disappear BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I5fdf4de0383ef373dd45e8d8741aa861c9c4bdc6 --- M src/soc/mediatek/mt8186/rtc.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59653/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fdf4de0383ef373dd45e8d8741aa861c9c4bdc6 Gerrit-Change-Number: 59653 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
by Kane Chen (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Kangheui Won, Isaac Lee, chris wang. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59558 ) Change subject: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/zork/variants/shuboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59558/comment/02f6b9db_0f9caae1 PS5, Line 2: fw_config > Can you work on using probe in devicetree like what's done in line 76-96 here? Hi Kangheui, We tried add audio setting and use probe in "devicetree.cb", but there will be some problems, so modify audio setting to "variant.c", as follows issue b:198689479 #comment17. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/59558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749 Gerrit-Change-Number: 59558 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Randy Wang <ifanw(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 07:22:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/thermal: Refactor thermal block to improve reusability
by Subrata Banik (Code Review) 25 Nov '21

25 Nov '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59509 ) Change subject: soc/intel/common/thermal: Refactor thermal block to improve reusability ...................................................................... soc/intel/common/thermal: Refactor thermal block to improve reusability This patch moves common thermal API between chipsets with thermal device as PCI device and thermal device behind PMC into common file (thermal_common.c). Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC Kconfig to select as applicable for underlying chipset. +------------------------------------------------------+--------------+ | Thermal Kconfig | SoC | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV | SKL/KBL, CNL | | | till ICL | +------------------------------------------------------+--------------+ | CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC | TGL onwards | | | ICL | +------------------------------------------------------+--------------+ Either of these two Kconfig internally selects CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59509 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/Makefile.inc D src/soc/intel/common/block/thermal/thermal.c A src/soc/intel/common/block/thermal/thermal_common.c A src/soc/intel/common/block/thermal/thermal_pci.c M src/soc/intel/common/block/thermal/thermal_pmc.c M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 10 files changed, 109 insertions(+), 110 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index ed0f5a3..8fed9e9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -94,7 +94,7 @@ select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET diff --git a/src/soc/intel/common/block/include/intelblocks/thermal.h b/src/soc/intel/common/block/include/intelblocks/thermal.h index aa3318c..d995cc7 100644 --- a/src/soc/intel/common/block/include/intelblocks/thermal.h +++ b/src/soc/intel/common/block/include/intelblocks/thermal.h @@ -3,6 +3,25 @@ #ifndef _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ #define _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ +#define MAX_TRIP_TEMP 205 +/* This is the safest default Trip Temp value */ +#define DEFAULT_TRIP_TEMP 50 + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) + /* Trip Point Temp = (LTT / 2 - 50 degree C) */ + #define GET_LTT_VALUE(x) (((x) + 50) * (2)) +#elif CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC) + /* + * Trip Point = T2L | T1L | T0L where T2L > T1L > T0L + * T2L = Bit 28:20 + * T1L = Bit 18:10 + * T0L = Bit 8:0 + */ + #define GET_LTT_VALUE(x) (((x) + 10) << 20 | ((x) + 5) << 10 | (x)) +#else + #error <Undefined: GET_LTT_VALUE macro> +#endif + /* Catastrophic Trip Point Enable */ #define PMC_PWRM_THERMAL_CTEN 0x150c /* Policy Lock-Down Bit */ @@ -30,6 +49,10 @@ /* PHL Lock */ #define PMC_PWRM_THERMAL_PHLC_PHLCLOCK (1 << 31) +/* Get PCH Thermal Trip from common chip config */ +uint8_t get_thermal_trip_temp(void); +/* PCH Low Temp Threshold (LTT) */ +uint32_t pch_get_ltt_value(void); /* Enable thermal sensor power management */ void pch_thermal_configuration(void); diff --git a/src/soc/intel/common/block/thermal/Kconfig b/src/soc/intel/common/block/thermal/Kconfig index b39c74c..7ab7240 100644 --- a/src/soc/intel/common/block/thermal/Kconfig +++ b/src/soc/intel/common/block/thermal/Kconfig @@ -4,9 +4,19 @@ help This option allows to configure PCH thermal registers for supported PCH. +config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV + bool + default n + select SOC_INTEL_COMMON_BLOCK_THERMAL + help + This option allows to configure PCH thermal registers using Thermal PCI device + for chipsets till Ice Lake PCH. + config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC bool default n + depends on !SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV + select SOC_INTEL_COMMON_BLOCK_THERMAL help This option allows to configure PCH thermal registers using PMC PWRMBASE for chipsets since Tiger Lake PCH. diff --git a/src/soc/intel/common/block/thermal/Makefile.inc b/src/soc/intel/common/block/thermal/Makefile.inc index 2a65219..cd71032 100644 --- a/src/soc/intel/common/block/thermal/Makefile.inc +++ b/src/soc/intel/common/block/thermal/Makefile.inc @@ -1,3 +1,5 @@ -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal_common.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) += thermal_pci.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC) += thermal_pmc.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal_common.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) += thermal_pci.c diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c deleted file mode 100644 index 6106c49..0000000 --- a/src/soc/intel/common/block/thermal/thermal.c +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/mmio.h> -#include <intelblocks/cfg.h> -#include <intelblocks/thermal.h> -#include <soc/pci_devs.h> - -#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c -#define CATASTROPHIC_TRIP_POINT_MASK 0x1ff -#define MAX_TRIP_TEMP 205 -/* This is the safest default Trip Temp value */ -#define DEFAULT_TRIP_TEMP 50 -/* Trip Point Temp = (LTT / 2 - 50 degree C) */ -#define GET_LTT_VALUE(x) (((x) + 50) * (2)) - -static uint8_t get_thermal_trip_temp(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->pch_thermal_trip; -} - -/* PCH Low Temp Threshold (LTT) */ -static uint32_t pch_get_ltt_value(void) -{ - uint8_t thermal_config; - - thermal_config = get_thermal_trip_temp(); - if (!thermal_config) - thermal_config = DEFAULT_TRIP_TEMP; - - if (thermal_config > MAX_TRIP_TEMP) - die("Input PCH temp trip is higher than allowed range!"); - - return GET_LTT_VALUE(thermal_config); -} - -/* Enable thermal sensor power management */ -void pch_thermal_configuration(void) -{ - uintptr_t thermalbar; - uintptr_t thermalbar_pm; - const struct device *dev; - struct resource *res; - - dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); - if (!dev) { - printk(BIOS_ERR, "ERROR: PCH_DEVFN_THERMAL device not found!\n"); - return; - } - - res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) { - printk(BIOS_ERR, "ERROR: PCH thermal device not found!\n"); - return; - } - - /* Get the base address of the resource */ - thermalbar = res->base; - - /* Get the required thermal address to write the register value */ - thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; - - /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ - clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value()); -} diff --git a/src/soc/intel/common/block/thermal/thermal_common.c b/src/soc/intel/common/block/thermal/thermal_common.c new file mode 100644 index 0000000..ba1ab06 --- /dev/null +++ b/src/soc/intel/common/block/thermal/thermal_common.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/cfg.h> +#include <intelblocks/thermal.h> + +/* Get PCH Thermal Trip from common chip config */ +uint8_t get_thermal_trip_temp(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->pch_thermal_trip; +} + +/* PCH Low Temp Threshold (LTT) */ +uint32_t pch_get_ltt_value(void) +{ + uint8_t thermal_config; + + thermal_config = get_thermal_trip_temp(); + if (!thermal_config) + thermal_config = DEFAULT_TRIP_TEMP; + + if (thermal_config > MAX_TRIP_TEMP) + die("Input PCH temp trip is higher than allowed range!"); + + return GET_LTT_VALUE(thermal_config); +} diff --git a/src/soc/intel/common/block/thermal/thermal_pci.c b/src/soc/intel/common/block/thermal/thermal_pci.c new file mode 100644 index 0000000..1b9f28a --- /dev/null +++ b/src/soc/intel/common/block/thermal/thermal_pci.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <device/mmio.h> +#include <intelblocks/thermal.h> +#include <soc/pci_devs.h> + +#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c +#define CATASTROPHIC_TRIP_POINT_MASK 0x1ff + +/* Enable thermal sensor power management */ +void pch_thermal_configuration(void) +{ + uintptr_t thermalbar; + uintptr_t thermalbar_pm; + const struct device *dev; + struct resource *res; + + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + if (!dev) { + printk(BIOS_ERR, "ERROR: PCH_DEVFN_THERMAL device not found!\n"); + return; + } + + res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "ERROR: PCH thermal device not found!\n"); + return; + } + + /* Get the base address of the resource */ + thermalbar = res->base; + + /* Get the required thermal address to write the register value */ + thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; + + /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ + clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value()); +} diff --git a/src/soc/intel/common/block/thermal/thermal_pmc.c b/src/soc/intel/common/block/thermal/thermal_pmc.c index d233e9d..3525b47 100644 --- a/src/soc/intel/common/block/thermal/thermal_pmc.c +++ b/src/soc/intel/common/block/thermal/thermal_pmc.c @@ -1,46 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/mmio.h> -#include <intelblocks/cfg.h> #include <intelblocks/pmclib.h> #include <intelblocks/thermal.h> -#define MAX_TRIP_TEMP 205 -/* This is the safest default Trip Temp value */ -#define DEFAULT_TRIP_TEMP 50 - -/* - * Trip Point = T2L | T1L | T0L where T2L > T1L > T0L - * T2L = Bit 28:20 - * T1L = Bit 18:10 - * T0L = Bit 8:0 - */ -#define GET_LTT_VALUE(x) ((x + 10) << 20 | (x + 5) << 10 | x) - -static uint8_t get_thermal_trip_temp(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->pch_thermal_trip; -} - -/* PCH Low Temp Threshold (LTT) */ -static uint32_t pch_get_ltt_value(void) -{ - uint8_t thermal_config; - - thermal_config = get_thermal_trip_temp(); - if (!thermal_config) - thermal_config = DEFAULT_TRIP_TEMP; - - if (thermal_config > MAX_TRIP_TEMP) - die("Input PCH temp trip is higher than allowed range!"); - - return GET_LTT_VALUE(thermal_config); -} - /* * Thermal configuration has evolved over time. With older platform the * thermal device is sitting over PCI and allow to configure its configuration diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index e99832d..999bc9d 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -50,7 +50,7 @@ select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0df1611..b90fdef 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -70,7 +70,7 @@ select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6 Gerrit-Change-Number: 59509 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/i2c: Return negative values on error
by Yu-Ping Wu (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Paul Menzel, Felix Held. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59539 ) Change subject: soc/mediatek/i2c: Return negative values on error ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: Done. > so the proper fix would be to make platform_i2c_transfer return a negative value in those failure cases, so that the same bug can't happen in other drivers However, note that there are many existing calls to i2c_*() that assume errors when receiving non-zero return values: if (i2c_writeb(...)) printk(BIOS_ERR, ...); -- To view, visit https://review.coreboot.org/c/coreboot/+/59539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Gerrit-Change-Number: 59539 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wei-Shun Chang <weishunc(a)google.com> Gerrit-Reviewer: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Nov 2021 07:16:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit November 2021