coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Shon Wang (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Kevin Chiu, YH Lin, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Nick Vaccaro, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59334 to look at the new patch set (#11). Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... mb/google/brya/var/vell: update memory settings BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/vell/Makefile.inc A src/mainboard/google/brya/variants/vell/memory.c 2 files changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59334/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 11 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common/usb: Add support for common USB driver
by Sandeep Maheswaram (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Sandeep Maheswaram has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56091 ) Change subject: soc/qualcomm/common/usb: Add support for common USB driver ...................................................................... Patch Set 40: (9 comments) File src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h: https://review.coreboot.org/c/coreboot/+/56091/comment/034497ef_835389c2 PS38, Line 15: > Don't put random blank lines in struct definitions. Done File src/soc/qualcomm/common/include/soc/usb/qusb_phy.h: https://review.coreboot.org/c/coreboot/+/56091/comment/3b8c2d79_2db198a3 PS38, Line 43: //#define USB3_PCS_PHYSTATUS BIT(6) > No commented-out code Done File src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h: https://review.coreboot.org/c/coreboot/+/56091/comment/c8280eec_cfb5a0af PS38, Line 14: > spurious newline Done File src/soc/qualcomm/common/usb/qmpv3_usb_phy.c: https://review.coreboot.org/c/coreboot/+/56091/comment/dd00f2d0_7c453323 PS38, Line 358: = { > Don't put the = on a new line. Done File src/soc/qualcomm/common/usb/qmpv4_usb_phy.c: https://review.coreboot.org/c/coreboot/+/56091/comment/0d21f461_7be8a753 PS38, Line 352: = { > same Done File src/soc/qualcomm/common/usb/qusb_phy.c: https://review.coreboot.org/c/coreboot/+/56091/comment/6ae7fab6_2de608be PS38, Line 6: void hs_usb_phy_init(void *board_data); > This prototype is already in usb_common.h, just include that instead. Done https://review.coreboot.org/c/coreboot/+/56091/comment/89018a2e_4f28bf10 PS38, Line 11: > same here Done https://review.coreboot.org/c/coreboot/+/56091/comment/8ff8fba8_2339ed1e PS38, Line 27: > Please try to be somewhat consistent with the continuation line indentation. Done File src/soc/qualcomm/common/usb/snps_usb_phy.c: https://review.coreboot.org/c/coreboot/+/56091/comment/2a318331_e428fe4f PS38, Line 33: void hs_usb_phy_init(void *board_data); > same here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Gerrit-Change-Number: 56091 Gerrit-PatchSet: 40 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 11:02:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc: Add dram information to cbmem
by Ravi kumar (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, mturney mturney, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59195 to look at the new patch set (#5). Change subject: soc: Add dram information to cbmem ...................................................................... soc: Add dram information to cbmem BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 --- M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59195/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/lib: Add CBMEM tag id to parse ddr information
by Ravi kumar (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, mturney mturney, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59194 to look at the new patch set (#5). Change subject: src/lib: Add CBMEM tag id to parse ddr information ...................................................................... src/lib: Add CBMEM tag id to parse ddr information BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f --- M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 3 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/59194/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f Gerrit-Change-Number: 59194 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/herobrine: Initialize USB by calling SOC method
by Ravi kumar (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56093 to look at the new patch set (#40). Change subject: mb/google/herobrine: Initialize USB by calling SOC method ...................................................................... mb/google/herobrine: Initialize USB by calling SOC method Initialize by calling `setup_usb_host0()` from SOC code BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 --- M src/mainboard/google/herobrine/mainboard.c M src/mainboard/google/herobrine/romstage.c 2 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56093/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/56093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Gerrit-Change-Number: 56093 Gerrit-PatchSet: 40 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common/usb: Add support for common USB driver
by Ravi kumar (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Ravi kumar, Sandeep Maheswaram, Paul Menzel, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56091 to look at the new patch set (#40). Change subject: soc/qualcomm/common/usb: Add support for common USB driver ...................................................................... soc/qualcomm/common/usb: Add support for common USB driver Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 --- M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/trogdor/romstage.c A src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/qusb_phy.h A src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/usb_common.h R src/soc/qualcomm/common/usb/qmpv3_usb_phy.c A src/soc/qualcomm/common/usb/qmpv4_usb_phy.c A src/soc/qualcomm/common/usb/qusb_phy.c A src/soc/qualcomm/common/usb/snps_usb_phy.c A src/soc/qualcomm/common/usb/usb.c M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/include/soc/usb.h 13 files changed, 1,009 insertions(+), 417 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56091/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/56091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Gerrit-Change-Number: 56091 Gerrit-PatchSet: 40 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59086 ) Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... Patch Set 12: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59086/comment/9c2465b2_5f816dc4 PS7, Line 9: The Realtek RT8168 and RT8125 have a similar programming : interface, therefore add the PCI device ID for the RT8125 : into driver for support. > Please reflow for 75 characters per line. Fixed. https://review.coreboot.org/c/coreboot/+/59086/comment/2ba2f498_aa420bea PS7, Line 14: TEST=emerge-brask coreboot chromeos-bootimage > Oh, google/brask. Still the second questions remains. Added the testing detail in the message. Patchset: PS5: > separate commit? Yes. We are now working on LED part in commit https://review.coreboot.org/c/coreboot/+/59531. File src/drivers/net/r8168.c: https://review.coreboot.org/c/coreboot/+/59086/comment/b25b24bd_76860ba2 PS4, Line 255: /* : * Refer to RTL8111H datasheet 7.2 Customizable LED Configuration : * Starting from offset 0x18 : * Bit[15:12] LED Feature Control(FC) : * Bit[11:08] LED Select for PINLED2 : * Bit[07:04] LED Select for PINLED1 : * Bit[03:00] LED Select for PINLED0 : * : * Speed Link10M Link100M Link1000M ACT/Full : * LED0 Bit0 Bit1 Bit2 Bit3 : * LED1 Bit4 Bit5 Bit6 Bit7 : * LED2 Bit8 Bit9 Bit10 Bit11 : * FC Bit12 Bit13 Bit14 Bit15 : */ : : /* Set customized LED registers */ : outw(config->customized_leds, io_base + CMD_LED0_LED1); > This is incorrect for the 8125. […] Yes. We are now working on this in commit https://review.coreboot.org/c/coreboot/+/59531. File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/59086/comment/812a8ed5_490730b4 PS7, Line 1287: #define PCI_DEVICE_ID_REALTEK_8125 0x8125 > Please sort them. Sorted. -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 12 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:56:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Allow platforms without FIT enable Intel TXT
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59518 ) Change subject: security/intel/txt: Allow platforms without FIT enable Intel TXT ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59518/comment/99e7ed16_3a0fd1fa PS7, Line 7: enable nit: `to use` (`to enable` also works, but is longer) -- To view, visit https://review.coreboot.org/c/coreboot/+/59518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2858c8de9396449a0ee30837a98fab05570a6259 Gerrit-Change-Number: 59518 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:55:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc: Added dram information to cbmem
by Ravi Kumar Bokka (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: soc: Added dram information to cbmem ...................................................................... Patch Set 4: (5 comments) File src/soc/qualcomm/common/include/soc/mmu_common.h: https://review.coreboot.org/c/coreboot/+/59195/comment/05fe712a_9b3ad00c PS3, Line 13: static struct region * const ddr_region = (struct region *)_ddr_information; > We don't need ddr_region anymore because mem_chip_info contains the same information (and more). […] We will removew once mem_chip_info is squared away, this is temporarily on hold. https://review.coreboot.org/c/coreboot/+/59195/comment/5c5b05cd_dbdaee87 PS3, Line 14: struct region > This isn't a struct region, this is the mem_chip_info struct (which you should define somewhere in s […] Done File src/soc/qualcomm/common/include/soc/qclib_common.h: https://review.coreboot.org/c/coreboot/+/59195/comment/8d33eb8d_f92f13c7 PS3, Line 25: /* memchip info */ > This comment adds absolutely nothing useful to this code. Done File src/soc/qualcomm/common/qclib.c: https://review.coreboot.org/c/coreboot/+/59195/comment/d5900e9d_f56fbdf6 PS3, Line 27: #if TEST_CODE /* Added this structure for testing purpose, will be remove once changes are reviewd */ > Please clean this stuff up so we can properly read the file. Done File src/soc/qualcomm/sc7280/memlayout.ld: https://review.coreboot.org/c/coreboot/+/59195/comment/b6b2a27c_94017a16 PS3, Line 51: REGION(mem_chip_info, 0x1494E000, 1K, 1K) /* memchip info */ > I don't really think we need to put this in a separate SRAM region anymore. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:54:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: David Wu, Rory Liu, Zhuohao Lee, Alan Huang. Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59086 to look at the new patch set (#12). Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... drivers/net/r8168: Add support for Realtek RT8125 The Realtek RT8168 and RT8125 have a similar programming interface, therefore add the PCI device ID for the RT8125 into driver for support. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC is RT8125. Check if the default MAC is written into the NIC. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 --- M src/drivers/net/r8168.c M src/include/device/pci_ids.h 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 12 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021