coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59596 ) Change subject: soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO ...................................................................... soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO Stoneyridge uses the same GPIO bank peripheral as Picasso and Cezanne so we can use the common AMD SoC GPIO ACPI code. TEST=none Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59596 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/acpi.c 2 files changed, 1 insertion(+), 100 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 50e66b0..769a615 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -24,6 +24,7 @@ select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_AOAC diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 918ba5e..b2cc20b 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -157,103 +157,3 @@ acpigen_write_name_integer("PCNT", cores); acpigen_pop_len(); } - -static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) -{ - /* - * Store (\_SB.GPR2 (addr), Local5) - * \_SB.GPR2 is used to read control byte 2 from control register. - * / It is defined in gpio_lib.asl. - */ - acpigen_write_store(); - acpigen_emit_namestring("\\_SB.GPR2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); -} - -static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - uintptr_t addr = gpio_get_address(gpio_num); - - acpigen_soc_get_gpio_in_local5(addr); - - /* If (And (Local5, mask)) */ - acpigen_write_if_and(LOCAL5_OP, mask); - - /* Store (One, Local0) */ - acpigen_write_store_ops(ONE_OP, LOCAL0_OP); - - /* Else */ - acpigen_write_else(); - - /* Store (Zero, Local0) */ - acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); - - acpigen_pop_len(); /* Else */ - - return 0; -} - -static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - uintptr_t addr = gpio_get_address(gpio_num); - - /* Store (0x40, Local0) */ - acpigen_write_store(); - acpigen_write_integer(GPIO_PIN_OUT); - acpigen_emit_byte(LOCAL0_OP); - - acpigen_soc_get_gpio_in_local5(addr); - - if (val) { - /* Or (Local5, GPIO_PIN_OUT, Local5) */ - acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); - } else { - /* Not (GPIO_PIN_OUT, Local6) */ - acpigen_write_not(LOCAL0_OP, LOCAL6_OP); - - /* And (Local5, Local6, Local5) */ - acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); - } - - /* - * SB.GPW2 (addr, Local5) - * \_SB.GPW2 is used to write control byte in control register - * / byte 2. It is defined in gpio_lib.asl. - */ - acpigen_emit_namestring("\\_SB.GPW2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); - - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_set_gpio_val(gpio_num, 1); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_set_gpio_val(gpio_num, 0); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/59596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a Gerrit-Change-Number: 59596 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: superio/smsc/sch5545: Fix KBD and Runtime Registers init
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59524 ) Change subject: superio/smsc/sch5545: Fix KBD and Runtime Registers init ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59524/comment/bb202aa3_836dac2f PS3, Line 17: be always nit: `always be` File src/superio/smsc/sch5545/superio.c: https://review.coreboot.org/c/coreboot/+/59524/comment/d7333bf1_ac86eab0 PS3, Line 68: pnp_write_config(dev, 0xf0, pnp_read_config(dev, 0xf0) & 0x9f); How about: pnp_unset_and_set_config(dev, 0xf0, 3 << 5, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/59524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I790cac3ce1101565b64ed54d9c6b50f5e9aa4cf6 Gerrit-Change-Number: 59524 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Nov 2021 11:08:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defs
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59595 ) Change subject: soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defs ...................................................................... soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defs De-duplicate the definitions for the pin status bit and use this new definition in both the C and the ACPI code. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59595 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 2 files changed, 3 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 5a13d8d..579ff68 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -159,7 +159,7 @@ { VAL0, 32 } - Local0 = (GPIO_INPUT_VALUE & VAL0) >> GPIO_INPUT_SHIFT + Local0 = (GPIO_PIN_STS & VAL0) >> GPIO_PIN_STS_SHIFT Return (Local0) } diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index ffc90ed..7345dd1 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -54,15 +54,13 @@ #define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) #define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_PIN_STS (1 << 16) +#define GPIO_PIN_STS_SHIFT 16 +#define GPIO_PIN_STS (1 << GPIO_PIN_STS_SHIFT) #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) #define GPIO_PULL_MASK (GPIO_PULLUP_ENABLE | GPIO_PULLDOWN_ENABLE) -#define GPIO_INPUT_SHIFT 16 -#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) - #define GPIO_OUTPUT_SHIFT 22 #define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) #define GPIO_OUTPUT_ENABLE (1 << 23) -- To view, visit https://review.coreboot.org/c/coreboot/+/59595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552 Gerrit-Change-Number: 59595 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defs
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59594 ) Change subject: soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defs ...................................................................... soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defs The GPIO_WAKE_* definitions are the ones that are used in the code, so drop the unused GPIO_*_WAKE_EN definitions for the same bits. Also move the GPIO_WAKE_* definitions to the place the GPIO_*_WAKE_EN ones were before this patch. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I622673cc72107908b525a65212061062f32e13dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59594 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 7 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 3d97250..ffc90ed 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -46,9 +46,13 @@ #define GPIO_INT_ENABLE_STATUS_DELIVERY (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) #define GPIO_INT_ENABLE_MASK (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) -#define GPIO_S0I3_WAKE_EN (1 << 13) -#define GPIO_S3_WAKE_EN (1 << 14) -#define GPIO_S4_S5_WAKE_EN (1 << 15) +#define GPIO_WAKE_S0i3 (1 << 13) +#define GPIO_WAKE_S3 (1 << 14) +#define GPIO_WAKE_S4_S5 (1 << 15) +#define GPIO_WAKE_S0i3_S3 (GPIO_WAKE_S0i3 | GPIO_WAKE_S3) +#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) #define GPIO_PIN_STS (1 << 16) @@ -130,14 +134,6 @@ #define GPIO_DEB_MASK 0xff -#define GPIO_WAKE_S0i3 (1 << 13) -#define GPIO_WAKE_S3 (1 << 14) -#define GPIO_WAKE_S4_S5 (1 << 15) -#define GPIO_WAKE_S0i3_S3 (GPIO_WAKE_S0i3 | GPIO_WAKE_S3) -#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) - /* * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` * Bits that are preserved/untouched: -- To view, visit https://review.coreboot.org/c/coreboot/+/59594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I622673cc72107908b525a65212061062f32e13dd Gerrit-Change-Number: 59594 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: use bit definitions for masks
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59593 ) Change subject: soc/amd/common/block/include/gpio_defs: use bit definitions for masks ...................................................................... soc/amd/common/block/include/gpio_defs: use bit definitions for masks All bits covered by the bit masks GPIO_INT_ENABLE_MASK, GPIO_PULL_MASK, GPIO_STATUS_MASK and GPIO_WAKE_MASK already have definitions in the code so use those instead of magic numbers. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59593 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 7ca1c00..3d97250 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -44,7 +44,7 @@ #define GPIO_INT_ENABLE_STATUS (1 << 11) #define GPIO_INT_ENABLE_DELIVERY (1 << 12) #define GPIO_INT_ENABLE_STATUS_DELIVERY (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) -#define GPIO_INT_ENABLE_MASK (3 << 11) +#define GPIO_INT_ENABLE_MASK (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) #define GPIO_S0I3_WAKE_EN (1 << 13) #define GPIO_S3_WAKE_EN (1 << 14) @@ -54,7 +54,7 @@ #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) -#define GPIO_PULL_MASK (3 << 20) +#define GPIO_PULL_MASK (GPIO_PULLUP_ENABLE | GPIO_PULLDOWN_ENABLE) #define GPIO_INPUT_SHIFT 16 #define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) @@ -66,7 +66,7 @@ #define GPIO_INT_STATUS (1 << 28) #define GPIO_WAKE_STATUS (1 << 29) -#define GPIO_STATUS_MASK (3 << 28) +#define GPIO_STATUS_MASK (GPIO_INT_STATUS | GPIO_WAKE_STATUS) #define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) #define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE @@ -136,7 +136,7 @@ #define GPIO_WAKE_S0i3_S3 (GPIO_WAKE_S0i3 | GPIO_WAKE_S3) #define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) #define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_MASK (7 << 13) +#define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) /* * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` -- To view, visit https://review.coreboot.org/c/coreboot/+/59593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648 Gerrit-Change-Number: 59593 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: remove unneeded line break
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59592 ) Change subject: soc/amd/common/block/include/gpio_defs: remove unneeded line break ...................................................................... soc/amd/common/block/include/gpio_defs: remove unneeded line break The definitions of GPIO_INT_ENABLE_STATUS_DELIVERY and GPIO_TIMEBASE_62440uS fit into 96 characters, so remove the unneeded line breaks. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59592 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 793e717..7ca1c00 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -43,8 +43,7 @@ #define GPIO_INT_ENABLE_STATUS (1 << 11) #define GPIO_INT_ENABLE_DELIVERY (1 << 12) -#define GPIO_INT_ENABLE_STATUS_DELIVERY \ - (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) +#define GPIO_INT_ENABLE_STATUS_DELIVERY (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) #define GPIO_INT_ENABLE_MASK (3 << 11) #define GPIO_S0I3_WAKE_EN (1 << 13) @@ -115,8 +114,7 @@ #define GPIO_TIMEBASE_61uS 0 #define GPIO_TIMEBASE_183uS (1 << 4) #define GPIO_TIMEBASE_15560uS (1 << 7) -#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ - GPIO_TIMEBASE_15560uS) +#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | GPIO_TIMEBASE_15560uS) #define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) #define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) #define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) -- To view, visit https://review.coreboot.org/c/coreboot/+/59592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7 Gerrit-Change-Number: 59592 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: drop 8k pullup define
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59591 ) Change subject: soc/amd/common/block/include/gpio_defs: drop 8k pullup define ...................................................................... soc/amd/common/block/include/gpio_defs: drop 8k pullup define The corresponding bit is marked as reserved in the following versions of the documentation for all SoCs using this code: Mullins: BKDG #52740 Rev 3.05 Stoneyridge: BKDG #55072 Rev 3.04 Raven1, Picasso: PPR #55570 Rev 3.16 & 3.18 Raven2: PPR #55772 Rev 3.08 Cezanne: PPR #56569 Rev 3.03 The old Rev 3.14 of the Picasso PPR #55570 had the bit 19 defined as PullUpSel, but this is no longer the case in newer versions. It is unclear if this got de-featured or if it was never present in the silicon. To be consistent with the current documentation, drop this define. This patch also change the definition of GPIO_PULL_MASK to only cover the bits used for the feature. The Cezanne PPR #56569 Rev 3.03 states a default value of 0 for this bit after reset, so the resulting values in the register aren't expected change. The other PPRs/BKDGs don't specify a reset value for this bit, but it's likely safe to assume that all SoCs that use the new GPIO interface use the same GPIO building block. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59591 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 2 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 757e0f2..793e717 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -52,10 +52,10 @@ #define GPIO_S4_S5_WAKE_EN (1 << 15) #define GPIO_PIN_STS (1 << 16) -#define GPIO_8KPULLUP_SELECT (1 << 19) + #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) -#define GPIO_PULL_MASK (7 << 19) +#define GPIO_PULL_MASK (3 << 20) #define GPIO_INPUT_SHIFT 16 #define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) @@ -72,7 +72,6 @@ #define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) #define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE -#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) #define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE #define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE #define GPIO_PULL_PULL_NONE 0 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33 Gerrit-Change-Number: 59591 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: drop 8k pullup define
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59591 ) Change subject: soc/amd/common/block/include/gpio_defs: drop 8k pullup define ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59591/comment/bd144411_bbbdbdfe PS1, Line 9: reserved in all SoCs > the Cezanne PPR has reset values for that bit and it's 0, so this patch shouldn't change the value t […] updated the commit message with the information from this and some internal discussion -- To view, visit https://review.coreboot.org/c/coreboot/+/59591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33 Gerrit-Change-Number: 59591 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 11:06:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs i...
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59519 ) Change subject: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs in CBFS ...................................................................... Patch Set 8: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59519/comment/133072df_e878f5a3 PS8, Line 18: SINTI typo: SINIT Patchset: PS8: We could use a flexible array member in `struct txt_heap_acm_element`, but this prevents using a struct for the BDR contents. We would need to use a "raw" data buffer instead of the current "struct of structs". File src/security/intel/txt/ramstage.c: https://review.coreboot.org/c/coreboot/+/59519/comment/d30988e3_dcf0c794 PS8, Line 320: nit: drop blank line -- To view, visit https://review.coreboot.org/c/coreboot/+/59519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e Gerrit-Change-Number: 59519 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 11:04:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by MartiniMoe (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Nico Huber, Paul Menzel, Kilian Neuner, Charles Moyes, Alexander Couzens. MartiniMoe has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: Hi, I was just wondering if anyone is still working on this or if this will ever get merged? I own a x230 with FHD Mod and would love to use Coreboot on it, but I'm not sure, if Coreboot would work on it if I just merge this on my own branch before compiling? Thanks anyway for your awesome work on this! 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 12 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kilian Neuner <cb(a)9-r.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Charles Moyes <thechuckster(a)gmail.com> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: MartiniMoe Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Stanislaw Kaminski <stanislaw.kaminski(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-CC: clayton craft Gerrit-CC: nullmark <nullmark(a)googlemail.com> Gerrit-CC: slact Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kilian Neuner <cb(a)9-r.net> Gerrit-Attention: Charles Moyes <thechuckster(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Thu, 25 Nov 2021 11:03:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021