coreboot-gerrit November 2021

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Change in coreboot[master]: security/intel/txt: Issue a global reset when TXT_RESET bit is set
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59639 ) Change subject: security/intel/txt: Issue a global reset when TXT_RESET bit is set ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ee2400fab20857ff89b14bb7b662a938b775304 Gerrit-Change-Number: 59639 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:54:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Use set_global_reset in txt_reset_platform if pos...
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59517 ) Change subject: security/intel/txt: Use set_global_reset in txt_reset_platform if possible ...................................................................... Patch Set 6: Code-Review+2 (2 comments) Commit Message: PS3: > Split into two: […] Thanks! File src/security/intel/txt/getsec.c: https://review.coreboot.org/c/coreboot/+/59517/comment/bf92ae2d_f5d6ff7c PS3, Line 71: txt_reset_platform(); > True. Reverted here. […] Yes, I didn't comment on that one because I also saw that it's what Intel RC does. -- To view, visit https://review.coreboot.org/c/coreboot/+/59517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I561458044860ee5a26f7d61bcff1c407fa1533f2 Gerrit-Change-Number: 59517 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:54:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Shon Wang (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Kevin Chiu, YH Lin, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Nick Vaccaro, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59334 to look at the new patch set (#10). Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... mb/google/brya/var/vell: update memory settings BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/vell/Makefile.inc A src/mainboard/google/brya/variants/vell/memory.c 2 files changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59334/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 10 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Correct reporting of chipset production fuse state
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59514 ) Change subject: security/intel/txt: Correct reporting of chipset production fuse state ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/security/intel/txt/common.c: https://review.coreboot.org/c/coreboot/+/59514/comment/584710fc_47e17b1a PS4, Line 222: if ((acm_header->flags & ACM_FORMAT_FLAGS_DEBUG) == : (read64((void *)TXT_VER_FSBIF) & TXT_VER_PRODUCTION_FUSED)) This check should also be updated, but note that it's incorrect. It returns a false negative when ACM is debug and chipset is production fused, because `(1 << 15) == (1 << 31)` is false. I'd do the following: const bool production_acm = !(acm_header->flags & ACM_FORMAT_FLAGS_DEBUG); if (production_acm != intel_txt_chipset_is_production_fused()) return ACM_E_PLATFORM_IS_NOT_PROD; -- To view, visit https://review.coreboot.org/c/coreboot/+/59514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86c5a9e1d162630a1cf61435d1014edabf104b0 Gerrit-Change-Number: 59514 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 10:50:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: David Wu, Rory Liu, Zhuohao Lee, Alan Huang. Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59086 to look at the new patch set (#11). Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... drivers/net/r8168: Add support for Realtek RT8125 The Realtek RT8168 and RT8125 have a similar programming interface, therefore add the PCI device ID for the RT8125 into driver for support. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC is RT8125. Check if the default MAC is written into the NIC. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 --- M src/drivers/net/r8168.c M src/include/device/pci_ids.h 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 11 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: move bustracker_init before watchdog resets again
by Rex-BC Chen (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59667 to look at the new patch set (#2). Change subject: soc/mediatek: move bustracker_init before watchdog resets again ...................................................................... soc/mediatek: move bustracker_init before watchdog resets again The checking register will be cleared after resetting, so we move bustracker dump before resetting again. TEST=bustracker shows status before watchdog resets BUG=b:207450135 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/bootblock.c M src/soc/mediatek/mt8195/soc.c 6 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59667/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Gerrit-Change-Number: 59667 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: David Wu, Rory Liu, Zhuohao Lee, Alan Huang. Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59086 to look at the new patch set (#10). Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... drivers/net/r8168: Add support for Realtek RT8125 The Realtek RT8168 and RT8125 have a similar programming interface, therefore add the PCI device ID for the RT8125 into driver for support. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage. Test along with CL:59531 on brask whose NIC is RT8125. Check if the default MAC is written into the NIC. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 --- M src/drivers/net/r8168.c M src/include/device/pci_ids.h 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 10 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Rory Liu <rory.liu(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59562 ) Change subject: soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value ...................................................................... soc/intel/adl: Modify SOC_INTEL_ALDERLAKE_DEBUG_CONSENT default value On ADL, we actually use debug consent 2 for soc debug by DBC Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59562 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 3 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2cbff00..e5d6d6b 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -289,7 +289,7 @@ int "Debug Consent for ADL" # USB DBC is more common for developers so make this default to 3 if # SOC_INTEL_DEBUG_CONSENT=y - default 3 if SOC_INTEL_DEBUG_CONSENT + default 2 if SOC_INTEL_DEBUG_CONSENT default 0 help This is to control debug interface on SOC. @@ -297,9 +297,8 @@ PlatformDebugConsent in FspmUpd.h has the details. Desired platform debug type are - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), - 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), - 6:Enable (2-wire DCI OOB), 7:Manual + 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), + 7:Manual config DATA_BUS_WIDTH int -- To view, visit https://review.coreboot.org/c/coreboot/+/59562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9 Gerrit-Change-Number: 59562 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/elkhartlake: Update SA DIDs Table
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59559 ) Change subject: soc/intel/elkhartlake: Update SA DIDs Table ...................................................................... soc/intel/elkhartlake: Update SA DIDs Table Update SA table as per latest EDS (Doc no: 601458). Add extra SKUs accordingly. Signed-off-by: Rick Lee <rick.lee(a)intel.com> Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59559 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Lean Sheng Tan Reviewed-by: Praveen HP <praveen.hodagatta.pranesh(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/elkhartlake/bootblock/report_platform.c 3 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Praveen HP: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index fc82c26..63b735f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3964,6 +3964,8 @@ #define PCI_DEVICE_ID_INTEL_EHL_ID_11 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_12 0x4518 #define PCI_DEVICE_ID_INTEL_EHL_ID_13 0x451A +#define PCI_DEVICE_ID_INTEL_EHL_ID_14 0x4536 +#define PCI_DEVICE_ID_INTEL_EHL_ID_15 0x451C #define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22 #define PCI_DEVICE_ID_INTEL_JSL_ID_2 0x4e26 #define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 45e1d42..572b417 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -403,6 +403,8 @@ PCI_DEVICE_ID_INTEL_EHL_ID_11, PCI_DEVICE_ID_INTEL_EHL_ID_12, PCI_DEVICE_ID_INTEL_EHL_ID_13, + PCI_DEVICE_ID_INTEL_EHL_ID_14, + PCI_DEVICE_ID_INTEL_EHL_ID_15, PCI_DEVICE_ID_INTEL_JSL_ID_1, PCI_DEVICE_ID_INTEL_JSL_ID_2, PCI_DEVICE_ID_INTEL_JSL_ID_3, diff --git a/src/soc/intel/elkhartlake/bootblock/report_platform.c b/src/soc/intel/elkhartlake/bootblock/report_platform.c index 8d93e4d..9cb32cc 100644 --- a/src/soc/intel/elkhartlake/bootblock/report_platform.c +++ b/src/soc/intel/elkhartlake/bootblock/report_platform.c @@ -42,6 +42,8 @@ { PCI_DEVICE_ID_INTEL_EHL_ID_11, "Elkhartlake SKU-11" }, { PCI_DEVICE_ID_INTEL_EHL_ID_12, "Elkhartlake SKU-12" }, { PCI_DEVICE_ID_INTEL_EHL_ID_13, "Elkhartlake SKU-13" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_14, "Elkhartlake SKU-14" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_15, "Elkhartlake SKU-15" }, }; static struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/59559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706 Gerrit-Change-Number: 59559 Gerrit-PatchSet: 3 Gerrit-Owner: Rick Lee <rick.lee(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Praveen HP <praveen.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: akino.liao(a)intel.com Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/primus: Update thermal table for primus
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59182 ) Change subject: mb/google/brya/var/primus: Update thermal table for primus ...................................................................... mb/google/brya/var/primus: Update thermal table for primus - Add 4 TEMP_SENSORs - Configure granularity of power limits BUG=b:200836803 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com> Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59182 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/primus/overridetree.cb 1 file changed, 14 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 6a064a7..61e24d8 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -78,21 +78,28 @@ device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[0].desc" = ""SSD"" + register "options.tsr[1].desc" = ""CHARGER"" + register "options.tsr[2].desc" = ""MEMORY"" + register "options.tsr[3].desc" = ""TYPEC"" + # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 90, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000), }" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), }" register "controls.power_limits" = "{ @@ -101,7 +108,7 @@ .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200, + .granularity = 250, }, .pl2 = { .min_power = 55000, -- To view, visit https://review.coreboot.org/c/coreboot/+/59182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d Gerrit-Change-Number: 59182 Gerrit-PatchSet: 10 Gerrit-Owner: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit November 2021