coreboot-gerrit November 2021

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Change in coreboot[master]: util/ifdtool/Makefile: Derive from Makefile.inc
by Patrick Georgi (Code Review) 25 Nov '21

25 Nov '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59669 ) Change subject: util/ifdtool/Makefile: Derive from Makefile.inc ...................................................................... util/ifdtool/Makefile: Derive from Makefile.inc Instead of maintaining two complete Makefiles, reuse the coreboot build system rules in the stand-alone Makefile. Change-Id: I5d894a1f079799478bce0bd200ac735097f3806b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/ifdtool/Makefile 1 file changed, 8 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/59669/1 diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index 473dc08..83d19b8 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -2,43 +2,26 @@ # # SPDX-License-Identifier: GPL-2.0-only -PROGRAM = ifdtool - CC ?= gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror -CFLAGS += -I../../src/commonlib/include -I../../src/commonlib/bsd/include -CFLAGS += -I../cbfstool/flashmap -CFLAGS += -include ../../src/commonlib/bsd/include/commonlib/bsd/compiler.h -CFLAGS += -D_DEFAULT_SOURCE # for endianness converting functions -LDFLAGS = -OBJS = ifdtool.o -OBJS += fmap.o -OBJS += kv_pair.o -OBJS += valstr.o +HOSTCC ?= $(CC) +HOSTCFLAGS ?= $(CFLAGS) +top := ../.. +objutil := .. +include Makefile.inc -all: dep $(PROGRAM) +PROGRAM=$(objutil)/ifdtool/ifdtool -$(PROGRAM): $(OBJS) - $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) +all: $(PROGRAM) clean: rm -f $(PROGRAM) *.o *~ .dependencies distclean: clean -dep: - @$(CC) $(CFLAGS) -MM *.c > .dependencies - -%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< - -%.o: ../cbfstool/flashmap/%.c - $(CC) $(CFLAGS) -c -o $@ $< - install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/bin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin -.PHONY: all clean distclean dep +.PHONY: all clean distclean install -- To view, visit https://review.coreboot.org/c/coreboot/+/59669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d894a1f079799478bce0bd200ac735097f3806b Gerrit-Change-Number: 59669 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/testing: Add ifdtool to tools to be tested
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Patrick Georgi. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59664 ) Change subject: util/testing: Add ifdtool to tools to be tested ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fbe37dc01e46022c5e6de5629eb99f6b86b0b14 Gerrit-Change-Number: 59664 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 11:21:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib: Add new TS for CSE firmware Sync
by Sridhar Siricilla (Code Review) 25 Nov '21

25 Nov '21

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59668 ) Change subject: commonlib: Add new TS for CSE firmware Sync ...................................................................... commonlib: Add new TS for CSE firmware Sync The patch defines new TS for CSE firmware synchronization. The cse_fw_sync() call sets CSE's boot partition and triggers CSE Firmware update. TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/59668/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index de3e1bb..ae57110 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -58,6 +58,8 @@ TS_READ_UCODE_END = 113, TS_ELOG_INIT_START = 114, TS_ELOG_INIT_END = 115, + TS_START_CSE_FW_SYNC = 116, + TS_END_CSE_FW_SYNC = 117, /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ TS_START_COPYVER = 501, @@ -204,6 +206,8 @@ { TS_READ_UCODE_END, "finished reading uCode" }, { TS_ELOG_INIT_START, "started elog init" }, { TS_ELOG_INIT_END, "finished elog init" }, + { TS_START_CSE_FW_SYNC, "Before cse_fw_sync"}, + { TS_END_CSE_FW_SYNC, "After cse_fw_sync"}, { TS_START_COPYVER, "starting to load verstage" }, { TS_END_COPYVER, "finished loading verstage" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/59668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a Gerrit-Change-Number: 59668 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Sridhar Siricilla (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Ravindra, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55364 to look at the new patch set (#13). Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init The patch enables cse_fw_sync() before DRAM initialization. cse_fw_sync() sends HECI commands in order to set CSE's boot partition and to trigger CSE firmware update. As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI command. Since CSE supports the command after DRAM Initialization, cse_fw_sync() is called after DRAM initialization. Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command before DRAM initialization too. So, cse_fw_sync() is called before DRAM initialization. BUG=b:175516533 TEST=Dependency with CSE Litev16.0.15.1545 integration Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 9 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/55364/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 13 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/cbmem_id.h: Add names for some IDs
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59617 ) Change subject: commonlib/cbmem_id.h: Add names for some IDs ...................................................................... commonlib/cbmem_id.h: Add names for some IDs Some IDs don't have an associated name. Add them. Change-Id: I1033dd0cecff417b65001f25f6cc4101b603bd9b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59617 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/include/commonlib/cbmem_id.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 5c90537..d150811 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -104,8 +104,10 @@ { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \ { CBMEM_ID_GDT, "GDT " }, \ { CBMEM_ID_HOB_POINTER, "HOB " }, \ + { CBMEM_ID_IGD_OPREGION, "IGD OPREGION" }, \ { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \ { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \ + { CBMEM_ID_MDATA_HASH, "METADATA HASH" }, \ { CBMEM_ID_MEMINFO, "MEM INFO " }, \ { CBMEM_ID_MMA_DATA, "MMA DATA " }, \ { CBMEM_ID_MMC_STATUS, "MMC STATUS " }, \ @@ -133,6 +135,7 @@ { CBMEM_ID_TCPA_TCG_LOG, "TCPA TCGLOG" }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ { CBMEM_ID_TPM2_TCG_LOG, "TPM2 TCGLOG" }, \ + { CBMEM_ID_TPM_PPI, "TPM PPI " }, \ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ @@ -147,5 +150,7 @@ { CBMEM_ID_FMAP, "FMAP "}, \ { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \ + { CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \ + { CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"} #endif /* _CBMEM_ID_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1033dd0cecff417b65001f25f6cc4101b603bd9b Gerrit-Change-Number: 59617 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: commonlib/cbmem_id.h: Fix typo in macro name
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59616 ) Change subject: commonlib/cbmem_id.h: Fix typo in macro name ...................................................................... commonlib/cbmem_id.h: Fix typo in macro name Rename `CMBMEM_ID_ACPI_HEST` to `CBMEM_ID_ACPI_HEST`. Change-Id: I3e680244c9573f566b51298462c324e062ab4657 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59616 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Patrick Georgi <patrick(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/include/commonlib/cbmem_id.h M src/soc/intel/xeon_sp/ras/hest.c 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index a9cf7bd..5c90537 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -7,7 +7,7 @@ #define CBMEM_ID_ACPI_BERT 0x42455254 #define CBMEM_ID_ACPI_CNVS 0x434e5653 #define CBMEM_ID_ACPI_GNVS 0x474e5653 -#define CMBMEM_ID_ACPI_HEST 0x48455354 +#define CBMEM_ID_ACPI_HEST 0x48455354 #define CBMEM_ID_ACPI_UCSI 0x55435349 #define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 @@ -85,7 +85,7 @@ { CBMEM_ID_ACPI_BERT, "ACPI BERT " }, \ { CBMEM_ID_ACPI_CNVS, "CHROMEOS NVS" }, \ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ - { CMBMEM_ID_ACPI_HEST, "ACPI HEST " }, \ + { CBMEM_ID_ACPI_HEST, "ACPI HEST " }, \ { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ { CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \ diff --git a/src/soc/intel/xeon_sp/ras/hest.c b/src/soc/intel/xeon_sp/ras/hest.c index 6164edf..02a9ab1 100644 --- a/src/soc/intel/xeon_sp/ras/hest.c +++ b/src/soc/intel/xeon_sp/ras/hest.c @@ -75,7 +75,7 @@ acpi_hest_t *hest; /* Reserve memory for Enhanced error logging */ - void *mem = cbmem_add(CMBMEM_ID_ACPI_HEST, CONFIG_ERROR_LOG_BUFFER_SIZE); + void *mem = cbmem_add(CBMEM_ID_ACPI_HEST, CONFIG_ERROR_LOG_BUFFER_SIZE); if (!mem) { printk(BIOS_ERR, "Unable to allocate HEST memory\n"); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/59616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e680244c9573f566b51298462c324e062ab4657 Gerrit-Change-Number: 59616 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/gpio: drop unused gpio_get_address
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59599 ) Change subject: soc/amd/common/block/gpio: drop unused gpio_get_address ...................................................................... soc/amd/common/block/gpio: drop unused gpio_get_address Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5b47324af368f81288e9e9be65fe0f1ae2fa3697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59599 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/gpio/gpio.c M src/soc/amd/common/block/include/amdblocks/gpio.h 2 files changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/gpio/gpio.c b/src/soc/amd/common/block/gpio/gpio.c index 1141846..163de2d 100644 --- a/src/soc/amd/common/block/gpio/gpio.c +++ b/src/soc/amd/common/block/gpio/gpio.c @@ -125,11 +125,6 @@ configure_scimap(&sci); } -uintptr_t gpio_get_address(gpio_t gpio_num) -{ - return (uintptr_t)gpio_ctrl_ptr(gpio_num); -} - static void gpio_update32(gpio_t gpio_num, uint32_t mask, uint32_t or) { uint32_t reg; diff --git a/src/soc/amd/common/block/include/amdblocks/gpio.h b/src/soc/amd/common/block/include/amdblocks/gpio.h index 21b73f7..7e6df9f 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio.h @@ -75,9 +75,6 @@ const struct soc_amd_gpio *override_cfg, size_t override_num_pads); -/* Get the address of the control register of a particular pin */ -uintptr_t gpio_get_address(gpio_t gpio_num); - /** * @brief program a particular set of GPIO * -- To view, visit https://review.coreboot.org/c/coreboot/+/59599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b47324af368f81288e9e9be65fe0f1ae2fa3697 Gerrit-Change-Number: 59599 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/acpi/gpio_bank_lib: drop unused methods
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59598 ) Change subject: soc/amd/common/acpi/gpio_bank_lib: drop unused methods ...................................................................... soc/amd/common/acpi/gpio_bank_lib: drop unused methods Those methods were only in the non-common Stoneyridge GPIO ACPI code that got dropped, so drop those unused methods too. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59598 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/acpi/gpio_bank_lib.asl 1 file changed, 0 insertions(+), 84 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 579ff68..eba263e 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -36,90 +36,6 @@ TEMP = Arg1 } -Method (GPGB, 0x2) -{ - /* - * Returns the desired byte - * Arg0 - GPIO pin control MMIO address - * Arg1 - Desired byte (0 through 3) - */ - Local2 = Arg1 * 8 - Return ((GPRD (Arg0) >> Local2) & 0x000000FF) -} - -Method (GPSB, 0x3) -{ - /* - * Reads dword, replace byte, write back dword - * Arg0 - GPIO pin control MMIO address - * Arg1 - Desired byte (0 through 3) - * Arg2 - Value - */ - Local2 = Arg1 * 8 - Local3 = (GPRD(Arg0) >> Local2) & 0xFFFFFF00 - Local4 = ((Arg2 & 0x000000FF) | Local3) << Local2 - GPWR (Arg0, Local4) -} - -/* Read pin control byte 0 */ -Method (GPR0, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 0)) -} - -/* Read pin control byte 1 */ -Method (GPR1, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 1)) -} - -/* Read pin control byte 2 */ -Method (GPR2, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 2)) -} - -/* Read pin control byte 3 */ -Method (GPR3, 0x1) -{ - Return (GPGB(Arg0, 3)) -} - -/* Write pin control byte 0 */ -Method (GPW0, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 0, Arg1) -} - -/* Write pin control byte 1 */ -Method (GPW1, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 1, Arg1) -} - -/* Write pin control byte 2 */ -Method (GPW2, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 2, Arg1) -} - -/* Write pin control byte 3 */ -Method (GPW3, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 3, Arg1) -} - /* * Set GPIO Output Value * Arg0 - GPIO Number -- To view, visit https://review.coreboot.org/c/coreboot/+/59598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2 Gerrit-Change-Number: 59598 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map
by Angel Pons (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Michał Żygowski, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59525 ) Change subject: mb/dell/optiplex_9010/romstage.c: Add interrupt routing map ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: Does the new routing improve anything? -- To view, visit https://review.coreboot.org/c/coreboot/+/59525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54 Gerrit-Change-Number: 59525 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 25 Nov 2021 11:09:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/include/gpio_defs: drop unused GPIO_PIN_IN/OUT
by Felix Held (Code Review) 25 Nov '21

25 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59597 ) Change subject: soc/amd/common/block/include/gpio_defs: drop unused GPIO_PIN_IN/OUT ...................................................................... soc/amd/common/block/include/gpio_defs: drop unused GPIO_PIN_IN/OUT Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Idf00879701b223ecaca74aef2a51a1b86d2c6ce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59597 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 7345dd1..d8da8b3 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -13,9 +13,6 @@ #define GPIO_IRQ_STAT_0 0x2f8 #define GPIO_IRQ_STAT_1 0x2fc -#define GPIO_PIN_IN (1 << 0) /* for byte access */ -#define GPIO_PIN_OUT (1 << 6) /* for byte access */ - /* Pad trigger type - Level or Edge */ #define GPIO_TRIGGER_EDGE (0 << 8) #define GPIO_TRIGGER_LEVEL (1 << 8) -- To view, visit https://review.coreboot.org/c/coreboot/+/59597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf00879701b223ecaca74aef2a51a1b86d2c6ce3 Gerrit-Change-Number: 59597 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021