Attention is currently required from: Hung-Te Lin, Yu-Ping Wu.
Hello Hung-Te Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59683
to look at the new patch set (#2).
Change subject: soc/mediatek: Flush cache before triggering EC reset
......................................................................
soc/mediatek: Flush cache before triggering EC reset
There will be no log on cbmem if we trigger ec reset on bootblock
stage. Therefore, call dcache_clean_all() before triggering ec
reset to flush cache to store logs on cbmem.
BUG=b:207743045
TEST=show logs on cbmem
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa
---
M 3rdparty/amd_blobs
M 3rdparty/blobs
M 3rdparty/intel-microcode
M 3rdparty/qc_blobs
M src/soc/mediatek/common/wdt.c
5 files changed, 7 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59683/2
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Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59306 )
Change subject: soc/intel/common: Include Alder Lake device IDs
......................................................................
Set Ready For Review
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Attention is currently required from: Henry Sun, Weimin Wu, Karthik Ramasubramanian.
Wizard Shen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59544 )
Change subject: mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetley
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59544/comment/2e633a84_df2ff8f4
PS2, Line 7: Enable Wifi SAR
> This change only enable GEO_SAR_ENABLE. […]
Thanks for correcting my problem.
Submitted content has been modified and confirm beetely enabled CHROMEOS_WIFI_SAR.
Patchset:
PS3:
> Because Blipper and Beetley use same BIOS,please conform that this SAR values match two project.
Blipper and Beetley use same BIOS, we retest this feature by RF engineer and the result is passed.This SAR values match two project.
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Attention is currently required from: Kevin Chiu, Paul Menzel, Tim Wawrzynczak, Wisley Chen.
Shon Wang has uploaded a new patch set (#6) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/59304 )
Change subject: mb/google/brya/var/vell: update overridetree
......................................................................
mb/google/brya/var/vell: update overridetree
Init basic override devicetree based on schematice
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Ibaa910eb1c5584197907963781258035c668298e
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
---
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/variants/vell/overridetree.cb
2 files changed, 377 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/59304/6
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Attention is currently required from: SH Kim.
Hello SH Kim,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/59684
to review the following change.
Change subject: mb/google/dedede/var/bugzzy: Configure LTE GPIOs using FW_CONFIG
......................................................................
mb/google/dedede/var/bugzzy: Configure LTE GPIOs using FW_CONFIG
The NC configurations for LTE GPIOs cannot disable LTE function
on LTE sku board by FW_CONFIG. This change sets LTE GPIO pads to
output low to ensure that LTE can be disabled by FW_CONFIG.
BUG=b:207805851
BRANCH=dedede
TEST=build firmware and see LTE can be disabled by FW_CONFIG
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
Change-Id: I01f4d3c623cb7f1deb6264cb88774788417d291d
---
M src/mainboard/google/dedede/variants/bugzzy/gpio.c
1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/59684/1
diff --git a/src/mainboard/google/dedede/variants/bugzzy/gpio.c b/src/mainboard/google/dedede/variants/bugzzy/gpio.c
index a218c5e..0066ae6 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/gpio.c
+++ b/src/mainboard/google/dedede/variants/bugzzy/gpio.c
@@ -56,9 +56,10 @@
};
static const struct pad_config lte_disable_pads[] = {
- PAD_NC(GPP_A10, NONE),
- PAD_NC(GPP_D0, NONE),
- PAD_NC(GPP_H17, NONE),
+
+ PAD_CFG_GPO(GPP_A10, 0, DEEP),
+ PAD_CFG_GPO(GPP_D0, 0, DEEP),
+ PAD_CFG_GPO(GPP_H17, 0, DEEP),
};
const struct pad_config *variant_override_gpio_table(size_t *num)
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 )
Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
......................................................................
Patch Set 14: Code-Review+2
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