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Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
Patch Set 9:
(7 comments)
File src/mainboard/google/brya/variants/vell/gpio.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134423):
https://review.coreboot.org/c/coreboot/+/59305/comment/0438e648_ce20eb2c
PS9, Line 151: /* B4 : PROC_GP3 ==> SSD_PERST_L */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134423):
https://review.coreboot.org/c/coreboot/+/59305/comment/2eca19ea_f18d8f92
PS9, Line 152: PAD_CFG_GPO(GPP_B4, 1, DEEP),
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134423):
https://review.coreboot.org/c/coreboot/+/59305/comment/51568b14_567d51e5
PS9, Line 152: PAD_CFG_GPO(GPP_B4, 1, DEEP),
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134423):
https://review.coreboot.org/c/coreboot/+/59305/comment/9ba6427d_d7b4fd02
PS9, Line 157: *num = ARRAY_SIZE(romstage_gpio_table);
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134423):
https://review.coreboot.org/c/coreboot/+/59305/comment/50c8a8c2_a873ef40
PS9, Line 157: *num = ARRAY_SIZE(romstage_gpio_table);
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134423):
https://review.coreboot.org/c/coreboot/+/59305/comment/6282bb67_750b8360
PS9, Line 158: return romstage_gpio_table;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134423):
https://review.coreboot.org/c/coreboot/+/59305/comment/63fc1124_00d7bdaa
PS9, Line 158: return romstage_gpio_table;
please, no spaces at the start of a line
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Shon Wang has uploaded a new patch set (#9) to the change originally created by Kevin Chiu. ( https://review.coreboot.org/c/coreboot/+/59305 )
Change subject: mb/google/brya/var/vell: update gpio override
......................................................................
mb/google/brya/var/vell: update gpio override
Configure GPIOs according to schematics
Update initial gpio configuration for redrix
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
---
A src/mainboard/google/brya/variants/vell/Makefile.inc
A src/mainboard/google/brya/variants/vell/gpio.c
2 files changed, 174 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59305/9
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Change subject: device/pci_device.c: Scan only one device for PCIe
......................................................................
Patch Set 3:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56788/comment/3c21157d_7edd671b
PS2, Line 9: device
> downstream port.
Done
https://review.coreboot.org/c/coreboot/+/56788/comment/dce7dbd4_37301cbb
PS2, Line 10:
> Please document the motivation in the commit message.
Done
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/56788/comment/873716d2_d62d9e12
PS2, Line 1208: 3.1
> nit: spec r5.0 also has this section 7.3. […]
Done
https://review.coreboot.org/c/coreboot/+/56788/comment/df1db16f_7b6663c9
PS2, Line 1226: if
> You don't really need an if here. It can be simply: […]
Done
https://review.coreboot.org/c/coreboot/+/56788/comment/4ed30eff_2cc1cb4a
PS2, Line 1228: PCI_EXP_TYPE_PCI_BRIDGE
> Yes, I made a mistake, this should be PCI_EXP_TYPE_PCIE_BRIDGE, thanks for the review.
Done
https://review.coreboot.org/c/coreboot/+/56788/comment/daa41fb2_2904af05
PS2, Line 1264: bus_only_one_child = pci_bus_only_one_child(bus);
> I am thinking that we should have a check here: […]
Done
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek: Enable PCIe support for mt8195
......................................................................
soc/mediatek: Enable PCIe support for mt8195
Enable PCIe support for mt8195.
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff
---
M src/soc/mediatek/mt8195/Kconfig
M src/soc/mediatek/mt8195/Makefile.inc
M src/soc/mediatek/mt8195/soc.c
3 files changed, 5 insertions(+), 0 deletions(-)
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Change subject: soc/mediatek: Add PCIe support
......................................................................
soc/mediatek: Add PCIe support
Add PCIe support for MediaTek platform and the prototype of pcicfg for
the platforms not support ECAM.
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0
---
M src/include/device/pci_mmio_cfg.h
A src/soc/mediatek/common/include/soc/pcie_common.h
A src/soc/mediatek/common/pcie.c
3 files changed, 376 insertions(+), 0 deletions(-)
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Change subject: device/pci_device.c: Scan only one device for PCIe
......................................................................
device/pci_device.c: Scan only one device for PCIe
Only scan one device if it's a PCIe downstream port.
A PCIe downstream port normally leads to a link with
only device 0 on it. As an optimization, scan only for
device 0 in that case.
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806
---
M src/device/pci_device.c
M src/include/device/pci_def.h
M src/include/device/pciexp.h
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Change subject: Revert "util/crossgcc: Update gcc to 11.2"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I may try to use UBSAN (General Setup -> Undefined behavior sanitizer support) to check if there's a […]
I just find some UBs with emulation/qemu-i440fx. I don't know whether there's one making coreboot unable to boot on real hardware.
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Change subject: mb/google/brya/var/vell: update memory settings
......................................................................
Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59334/comment/fa2df24e_3785edac
PS11, Line 8:
> Please elaborate, where you got these from.
Done
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Change subject: mb/google/brya/var/vell: update memory settings
......................................................................
mb/google/brya/var/vell: update memory settings
DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility
GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3
GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7
GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/vell/Makefile.inc
A src/mainboard/google/brya/variants/vell/memory.c
2 files changed, 103 insertions(+), 0 deletions(-)
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