coreboot-gerrit November 2021

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Change in coreboot[master]: soc/mediatek: move bustracker_init before watchdog resets again
by Rex-BC Chen (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has removed Xi Chen from this change. ( https://review.coreboot.org/c/coreboot/+/59667 ) Change subject: soc/mediatek: move bustracker_init before watchdog resets again ...................................................................... Removed reviewer Xi Chen. -- To view, visit https://review.coreboot.org/c/coreboot/+/59667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Gerrit-Change-Number: 59667 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/mediatek: Flush cache before triggering EC reset
by Rex-BC Chen (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59683 ) Change subject: soc/mediatek: Flush cache before triggering EC reset ...................................................................... soc/mediatek: Flush cache before triggering EC reset There will be no log on cbmem if we trigger ec reset on bootblock stage. Therefore, call dcache_clean_all() before triggering ec reset to flush cache to store logs on cbmem. BUG=b:207743045 TEST=show logs on cbmem Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa --- M src/soc/mediatek/common/wdt.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59683/1 diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index f06fbf0..ce1ccc3 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/cache.h> #include <device/mmio.h> #include <console/console.h> #include <soc/wdt.h> @@ -27,7 +28,10 @@ * We trigger secondary reset by triggering WDT hardware to send signal to EC. * We do not use do_board_reset() to send signal to EC * which is controlled by software driver. + * Before triggering secondary reset, flushing cache first to prevent there is + * log on cbmem. */ + dcache_clean_all(); write32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); } else if (wdt_sta & MTK_WDT_STA_SW_RST) -- To view, visit https://review.coreboot.org/c/coreboot/+/59683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa Gerrit-Change-Number: 59683 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: move bustracker_init before watchdog resets again
by Rex-BC Chen (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Yu-Ping Wu. Hello Xi Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59667 to look at the new patch set (#4). Change subject: soc/mediatek: move bustracker_init before watchdog resets again ...................................................................... soc/mediatek: move bustracker_init before watchdog resets again The checking register will be cleared after EC resets, so we move bustracker dump from ramstage to bootblock, before triggering EC reset. TEST=bustracker shows status before watchdog resets BUG=b:207743045 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/bootblock.c M src/soc/mediatek/mt8195/soc.c 6 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59667/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Gerrit-Change-Number: 59667 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by build bot (Jenkins) (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/retimer.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134432): https://review.coreboot.org/c/coreboot/+/59666/comment/19e323d2_61170da0 PS7, Line 31: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 26 Nov 2021 05:15:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement function to map physical port to EC port
by build bot (Jenkins) (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59666 ) Change subject: soc/intel/alderlake: Implement function to map physical port to EC port ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/retimer.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134431): https://review.coreboot.org/c/coreboot/+/59666/comment/62a7e0f0_aebb92ed PS6, Line 31: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/59666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3735b7c7794b46123aba3beac8c0268ce72d658c Gerrit-Change-Number: 59666 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 26 Nov 2021 05:15:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Maulik V Vaghela (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Sridhar Siricilla, Subrata Banik, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... Patch Set 14: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 14 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 26 Nov 2021 05:08:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: move bustracker_init before watchdog resets again
by Rex-BC Chen (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59667 ) Change subject: soc/mediatek: move bustracker_init before watchdog resets again ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59667/comment/2678e5fc_b8fe0afe PS2, Line 10: before resetting again > from ramstage to bootblock, before triggering watchdog Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Gerrit-Change-Number: 59667 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 26 Nov 2021 05:02:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: move bustracker_init before watchdog resets again
by Rex-BC Chen (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Rex-BC Chen. Hello Xi Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59667 to look at the new patch set (#3). Change subject: soc/mediatek: move bustracker_init before watchdog resets again ...................................................................... soc/mediatek: move bustracker_init before watchdog resets again The checking register will be cleared after EC resets, so we move bustracker dump from ramstage to bootblock, before triggering EC reset. TEST=bustracker shows status before watchdog resets BUG=b:207450135 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c M src/soc/mediatek/mt8192/soc.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/bootblock.c M src/soc/mediatek/mt8195/soc.c 6 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59667/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Gerrit-Change-Number: 59667 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Sridhar Siricilla (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... Patch Set 14: (2 comments) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/55364/comment/b9827a71_8dd10864 PS12, Line 145: cse_fw_sync() must be called after DRAM initialization as : * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) : * is expected to be executed after DRAM initialization. > Thanks for explanation and can you please write the same to the commit msg for record so folks don't […] Ack File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/55364/comment/063b221e_a9664571 PS13, Line 135: timestamp_add_now(TS_BEFORE_CSE_FW_SYNC); > nit: you can submit timestamp CL separately if you wish ? […] Correct , I will allow the original patch(without timestamp) land in upstream and also need clarification from community on TS ids to be used here. I will push cse fw sync timestamp patch separately once I get the feedback. -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 14 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 26 Nov 2021 04:20:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib: Add new TS for CSE firmware Sync
by Sridhar Siricilla (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Sridhar Siricilla. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59668 to look at the new patch set (#2). Change subject: commonlib: Add new TS for CSE firmware Sync ...................................................................... commonlib: Add new TS for CSE firmware Sync The patch defines new TS for CSE firmware synchronization. The cse_fw_sync() call sets CSE's boot partition and triggers CSE Firmware update. TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/59668/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a Gerrit-Change-Number: 59668 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021