Attention is currently required from: Ravi kumar.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58545 )
Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot.
......................................................................
Patch Set 11: Verified-1
(1 comment)
File src/soc/qualcomm/sc7280/soc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134454):
https://review.coreboot.org/c/coreboot/+/58545/comment/547bc546_d35fbf98
PS11, Line 27: if (soc_modem_carve_out(&start, &end))
that open brace { should be on the previous line
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Change subject: cbfs: Remove deprecated APIs
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59682/comment/d9f19a6f_b477d551
PS2, Line 10: new
Sorry I was not following this closely. What is the new API? Providing a CL link would be nice.
File src/security/vboot/Kconfig:
https://review.coreboot.org/c/coreboot/+/59682/comment/fc9e1e00_0f791f97
PS2, Line 254: CBFS will look for a file in the RO
: (COREBOOT) region
This reads a little bit weird to me, as the filesystem doesn't do it by itself. How about
a file in the RO (COREBOOT) region will be looked
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Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/herobrine: Initialize USB by calling SOC method
......................................................................
mb/google/herobrine: Initialize USB by calling SOC method
Initialize by calling `setup_usb_host0()` from SOC code
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org>
Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2
---
M src/mainboard/google/herobrine/mainboard.c
M src/mainboard/google/herobrine/romstage.c
2 files changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56093/41
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Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner,
I'd like you to reexamine a change. Please visit
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Change subject: soc/qualcomm/common/usb: Add support for common USB driver
......................................................................
soc/qualcomm/common/usb: Add support for common USB driver
Add common USB driver for qualcomm soc sc7180 and sc7280.
This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
---
M src/mainboard/google/trogdor/mainboard.c
M src/mainboard/google/trogdor/romstage.c
A src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h
A src/soc/qualcomm/common/include/soc/usb/qusb_phy.h
A src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h
A src/soc/qualcomm/common/include/soc/usb/usb_common.h
R src/soc/qualcomm/common/usb/qmpv3_usb_phy.c
A src/soc/qualcomm/common/usb/qmpv4_usb_phy.c
A src/soc/qualcomm/common/usb/qusb_phy.c
A src/soc/qualcomm/common/usb/snps_usb_phy.c
A src/soc/qualcomm/common/usb/usb.c
M src/soc/qualcomm/sc7180/Makefile.inc
D src/soc/qualcomm/sc7180/include/soc/usb.h
13 files changed, 1,005 insertions(+), 417 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56091/41
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Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59306 )
Change subject: soc/intel/common: Include Alder Lake-N device IDs
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59306/comment/e8ae097d_aba50317
PS2, Line 7: soc/intel/common: Include Alder Lake device IDs
> Alder Lake-N ?
Done
https://review.coreboot.org/c/coreboot/+/59306/comment/9fa4ed17_82e00b0f
PS2, Line 9: Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP),
> Alder Lake-N ?
Done
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Hello build bot (Jenkins), Maulik V Vaghela, Rizwan Qureshi, Reka Norman, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Balaji Manigandan, Tim Wawrzynczak, Patrick Rudolph, Kangheui Won,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: Include Alder Lake-N device IDs
......................................................................
soc/intel/common: Include Alder Lake-N device IDs
Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP),
IGD device IDs.
Document Number: 619501, 645548
Signed-off-by: Usha P <usha.p(a)intel.com>
Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86
---
M src/include/cpu/intel/cpu_ids.h
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/systemagent/systemagent.c
6 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/59306/3
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Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 )
Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
......................................................................
Patch Set 14: Code-Review+1
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Change subject: soc/intel/common: Include Alder Lake device IDs
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59306/comment/5ec11fa8_d05bacc9
PS2, Line 7: soc/intel/common: Include Alder Lake device IDs
Alder Lake-N ?
https://review.coreboot.org/c/coreboot/+/59306/comment/a010059e_428f158a
PS2, Line 9: Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP),
Alder Lake-N ?
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Hello Hung-Te Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59683
to look at the new patch set (#3).
Change subject: soc/mediatek: Flush cache before triggering EC reset
......................................................................
soc/mediatek: Flush cache before triggering EC reset
There will be no log on cbmem if we trigger ec reset on bootblock
stage. Therefore, call dcache_clean_all() before triggering ec
reset to flush cache to store logs on cbmem.
BUG=b:207743045
TEST=show logs on cbmem
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa
---
M src/soc/mediatek/common/wdt.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59683/3
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