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Change subject: soc/mediatek: Add PCIe support
......................................................................
Patch Set 3:
(1 comment)
File src/include/device/pci_mmio_cfg.h:
https://review.coreboot.org/c/coreboot/+/56791/comment/ca400ca7_860e3aec
PS3, Line 50: pcicfg
> Shelly, according to your design in CB:57861, I assume you will add this and rename it to pci_map_bu […]
If it's necessary to rename it to pci_map_bus(), I think I can send a patch to do it.
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Change subject: soc/mediatek/mt8195: Add driver to configure PCIe
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Removed Code-Review+2 by Yu-Ping Wu <yupingso(a)google.com>
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Change subject: soc/mediatek: Add PCIe support
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56791/comment/f0bf6f13_c44c6af4
PS3, Line 10: support
supporting
File src/include/device/pci_mmio_cfg.h:
https://review.coreboot.org/c/coreboot/+/56791/comment/14b297b2_0bd3a3d5
PS3, Line 50: pcicfg
Shelly, according to your design in CB:57861, I assume you will add this and rename it to pci_map_bus(). Do you want MTK to wait for your patch?
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Change subject: device/pci_device.c: Scan only one device for PCIe
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56788/comment/d88b37bc_315d2945
PS3, Line 11: A PCIe downstream port normally leads to a link with
: only device 0 on it. As an optimization, scan only for
: device 0 in that case.
Please reflow the text to match line length limit (72 chars).
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/56788/comment/70d20428_e2123ad6
PS3, Line 1207: A PCIe Downstream Port normally leads to a Link with only Device
: * 0 on it (PCIe spec r5.0, sec 7.3.1). As an optimization, scan
: * only for Device 0 in that situation.
Please reflow the text.
https://review.coreboot.org/c/coreboot/+/56788/comment/02a04caf_3209735e
PS3, Line 1260: 0x07
MIN(max_devfn, 0x07), as the passed max_devfn might be smaller than 0x07.
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Change subject: HACK: Herobrine: Reinit TPM INT gpio after qclib executes
......................................................................
Patch Set 36: Verified-1
(2 comments)
File src/soc/qualcomm/common/qclib.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134465):
https://review.coreboot.org/c/coreboot/+/57025/comment/beb033bc_6b6083ad
PS36, Line 254: mainboard_blob_fix();
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134465):
https://review.coreboot.org/c/coreboot/+/57025/comment/cdda3bbb_2acec959
PS36, Line 254: mainboard_blob_fix();
please, no spaces at the start of a line
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Change subject: soc/qualcomm/common/usb: Add support for common USB driver
......................................................................
Patch Set 41:
(4 comments)
File src/soc/qualcomm/common/include/soc/usb/qusb_phy.h:
https://review.coreboot.org/c/coreboot/+/56091/comment/71b015c4_9a8b5ac2
PS38, Line 95:
> same here
Done
File src/soc/qualcomm/common/usb/snps_usb_phy.c:
https://review.coreboot.org/c/coreboot/+/56091/comment/e3d75051_081cd510
PS38, Line 44: UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
> This can still fit on the previous line
Done
https://review.coreboot.org/c/coreboot/+/56091/comment/e7928fd5_d9892ab6
PS38, Line 48: POR, POR);
> This too (and many more times below).
Done
https://review.coreboot.org/c/coreboot/+/56091/comment/690b0e70_93be0424
PS38, Line 73: PARAM_OVRD_MASK, override_data->parameter_override_x2);
> What about parameter_override_x3?
Done
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Change subject: libpayload: Parse DDR Information through coreboot tables
......................................................................
Patch Set 6: Verified-1
(1 comment)
File payloads/libpayload/include/mem_chip_info.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134457):
https://review.coreboot.org/c/coreboot/+/59193/comment/e6a0df14_b5429e1b
PS6, Line 44: }dram_info;
space required after that close brace '}'
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