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Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions
......................................................................
Patch Set 15:
(2 comments)
Patchset:
PS15:
Removed psys_pmax_power from struct system_power_limits as the field is actually not used.
Added more comments in variants.h for function variants_update_psys_power_limits
File src/mainboard/google/brya/variants/baseboard/brask/ramstage.c:
https://review.coreboot.org/c/coreboot/+/58241/comment/683f729b_b0056f7d
PS14, Line 108: soc_config->tdp_pl4 = 0;
> You set tdp_pl4 to 0 here, which means you must call variant_update_psys_power_limits() first, then […]
Yes, it's correct. Added comments in variants.h.
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59518 )
Change subject: security/intel/txt: Allow platforms without FIT to use Intel TXT
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59518/comment/d3eb5b28_9bd91b99
PS7, Line 7: enable
> Seems like this was undone after the rebase.
Ahh, I thought I made sure to checkout newest version of this patch and cherry-pick the rest. Well, fixed again by in-gerrit commit message dition.
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Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#11).
Change subject: security/intel/txt: Allow platforms without FIT to use Intel TXT
......................................................................
security/intel/txt: Allow platforms without FIT to use Intel TXT
There is no real code or feature dependency on
CPU_INTEL_FIRMWARE_INTERFACE_TABLE for Intel TXT.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I2858c8de9396449a0ee30837a98fab05570a6259
---
M src/security/intel/txt/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59518/11
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Hello build bot (Jenkins), David Wu, Hou-hsun Lee, Tim Wawrzynczak, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/brask: Set PL and PsysPL
......................................................................
mb/google/brya/var/brask: Set PL and PsysPL
Set the defalut PL1, PL2 and PL4 according to Intel's spec.
Set PsysPL2 and PsysPmax according to Brask's spec.
BUG=b:193864533
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56
---
M src/mainboard/google/brya/variants/brask/Makefile.inc
A src/mainboard/google/brya/variants/brask/ramstage.c
2 files changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59576/2
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#15).
Change subject: mb/google/brya/var/baseboard/brask: Add power limits functions
......................................................................
mb/google/brya/var/baseboard/brask: Add power limits functions
Copy function variant_update_power_limits from brya to set power limits.
Add function variant_update_psys_power_limits and copy the algorithm
from puff. Add structure system_power_limits and psys_config to define
and config the psys power limits.
BUG=b:193864533
BRANCH=none
TEST=Build Pass
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248
---
M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
A src/mainboard/google/brya/variants/baseboard/brask/ramstage.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
3 files changed, 175 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/58241/15
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Hello Zheng Bao,
I'd like you to do a code review. Please visit
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to review the following change.
Change subject: [WIP]Cezanne FSP wrapper: Sync with PI 1.0.0.5
......................................................................
[WIP]Cezanne FSP wrapper: Sync with PI 1.0.0.5
New PI 1.0.0.5 has more data in hob of DMI. The coreboot also need to change.
BUG=b:204732649
Need to wait new FSP binary.
Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/vendorcode/amd/fsp/cezanne/dmi_info.h
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/59687/1
diff --git a/src/vendorcode/amd/fsp/cezanne/dmi_info.h b/src/vendorcode/amd/fsp/cezanne/dmi_info.h
index 304f387..d2c26fa 100644
--- a/src/vendorcode/amd/fsp/cezanne/dmi_info.h
+++ b/src/vendorcode/amd/fsp/cezanne/dmi_info.h
@@ -227,6 +227,9 @@
OUT UINT64 VolatileSize; ///< Size of the Volatile portion of the memory device in Bytes, if any.
OUT UINT64 CacheSize; ///< Size of the Cache portion of the memory device in Bytes, if any.
OUT UINT64 LogicalSize; ///< Size of the Logical memory device in Bytes.
+ // SMBIOS 3.3
+ OUT UINT32 ExtendedSpeed; ///< Extended Speed
+ OUT UINT32 ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed
} __packed TYPE17_DMI_INFO;
/// Collection of pointers to the DMI records
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59664 )
Change subject: util/testing: Add ifdtool to tools to be tested
......................................................................
util/testing: Add ifdtool to tools to be tested
Ensure that the separate Makefile doesn't break.
Change-Id: I0fbe37dc01e46022c5e6de5629eb99f6b86b0b14
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59664
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M util/testing/Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Felix Held: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc
index 0b93425..1411c7e 100644
--- a/util/testing/Makefile.inc
+++ b/util/testing/Makefile.inc
@@ -54,6 +54,7 @@
cbmem \
ectool \
futility \
+ifdtool \
intelmetool \
inteltool \
intelvbttool \
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59663 )
Change subject: util/ifdtool/Makefile: Fix building as standalone tool
......................................................................
util/ifdtool/Makefile: Fix building as standalone tool
Commit f1e401c6cb70 (util/cbfstool/flashmap/fmap.c: fix fmaptool
endianness bugs on BE) makes use of endianness conversion macros
in cbfstool's FMAP code, which is also used by ifdtool. At least
on Linux, the <endian.h> header provides these helpers, but only
when `__USE_MISC` is defined, which is defined in the <ctypes.h>
header when `_DEFAULT_SOURCE` is defined. This was accounted for
in `Makefile.inc`, but not in `Makefile`. As a result, trying to
build ifdtool as a standalone tool (i.e. not as part of building
a coreboot image) results in build errors because the endianness
conversion macros are not defined.
Define `_DEFAULT_SOURCE` in `Makefile` to fix the build errors.
Change-Id: I8c2bbc07ddd87d885e2d6f5c7f2bd501e5c4e3b0
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59663
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Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M util/ifdtool/Makefile
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
Paul Menzel: Looks good to me, but someone else must approve
Felix Held: Looks good to me, approved
Krystian Hebel: Looks good to me, but someone else must approve
diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
index e8d818c..473dc08 100644
--- a/util/ifdtool/Makefile
+++ b/util/ifdtool/Makefile
@@ -11,6 +11,7 @@
CFLAGS += -I../../src/commonlib/include -I../../src/commonlib/bsd/include
CFLAGS += -I../cbfstool/flashmap
CFLAGS += -include ../../src/commonlib/bsd/include/commonlib/bsd/compiler.h
+CFLAGS += -D_DEFAULT_SOURCE # for endianness converting functions
LDFLAGS =
OBJS = ifdtool.o
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51671 )
Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time
......................................................................
Patch Set 27:
(1 comment)
File src/ec/hp/kbc1126/Kconfig:
https://review.coreboot.org/c/coreboot/+/51671/comment/b66104db_2e60e017
PS27, Line 30: if KBC1126_FIRMWARE
> I'd much prefer to always add the `.ecfw_ptr` section, even when not adding the actual EC firmware (pointers would simply be invalid). This way, Jenkins will build-test it, and will catch build errors related to `.ecfw_ptr`.
I second this. 'if EC_HP_KBC1126' is better idea.
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Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time
......................................................................
Patch Set 27:
(3 comments)
File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/51671/comment/472b3dee_1e1c5f30
PS27, Line 355: present
nit: Missing a period
File src/arch/x86/bootblock.ld:
https://review.coreboot.org/c/coreboot/+/51671/comment/1618e69c_ff9a84cd
PS27, Line 57: _ID_SECTION_END = SIZEOF(.ecfw_ptr) && SIZEOF(.id) > _ID_SECTION_END - _ECFW_PTR ? _ECFW_PTR : _ID_SECTION_END;
Reposting my CB:51059 comment about this:
> .id exists for compatibility with legacy software. If it gets placed elsewhere, then it's like it wasn't anywhere to begin with.
File src/ec/hp/kbc1126/Kconfig:
https://review.coreboot.org/c/coreboot/+/51671/comment/b4971514_e13919c1
PS27, Line 30: if KBC1126_FIRMWARE
I'd much prefer to always add the `.ecfw_ptr` section, even when not adding the actual EC firmware (pointers would simply be invalid). This way, Jenkins will build-test it, and will catch build errors related to `.ecfw_ptr`.
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Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Comment-Date: Fri, 26 Nov 2021 10:05:57 +0000
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