coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/brask: Configurate the ISOLATE pin of LAN
by Alan Huang (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: David Wu, Zhuohao Lee. Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58105 to look at the new patch set (#7). Change subject: mb/google/brya/var/brask: Configurate the ISOLATE pin of LAN ...................................................................... mb/google/brya/var/brask: Configurate the ISOLATE pin of LAN Copy the default configuration from Puff. Update the 'stop_gpio' to GPP_H22. BUG=b:193750191 BRANCH=None TEST=Update kernel for 8125 outbox driver and test with command suspend_stress_test. Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/58105/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 7 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/brask: Enable LAN driver to write MAC
by Alan Huang (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Alan Huang. Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59087 to look at the new patch set (#2). Change subject: mb/google/brya/var/brask: Enable LAN driver to write MAC ...................................................................... mb/google/brya/var/brask: Enable LAN driver to write MAC Turn on the LAN device in devicetree and add Kconfig item RT8168_GET_MAC_FROM_VPD to support writting MAC address. BUG=b:193750191 BRANCH=None TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD. Use 'ifconfig' to check if the MAC written successfully. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/59087/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732 Gerrit-Change-Number: 59087 Gerrit-PatchSet: 2 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/i2c: Return negative values on error
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Paul Menzel, Yu-Ping Wu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59539 ) Change subject: soc/mediatek/i2c: Return negative values on error ...................................................................... Patch Set 3: Code-Review+2 (2 comments) File src/soc/mediatek/common/i2c.c: https://review.coreboot.org/c/coreboot/+/59539/comment/6b1ddf55_1020c219 PS3, Line 282: return ret; > Those enum values have been changed to negative in this patch. […] oh, sorry, somehow missed that part of the updated patch. yes, then this is correct https://review.coreboot.org/c/coreboot/+/59539/comment/add13139_cf574894 PS3, Line 317: if (ret < 0) > since mtk_i2c_transfer will return 0 or positive, this condition will always be false. […] missed the part of the patch that made the defined constants negative numbers, so this is correct -- To view, visit https://review.coreboot.org/c/coreboot/+/59539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Gerrit-Change-Number: 59539 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wei-Shun Chang <weishunc(a)google.com> Gerrit-Reviewer: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 26 Nov 2021 11:28:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool/Makefile: Derive from Makefile.inc
by Patrick Georgi (Code Review) 26 Nov '21

26 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59669 ) Change subject: util/ifdtool/Makefile: Derive from Makefile.inc ...................................................................... util/ifdtool/Makefile: Derive from Makefile.inc Instead of maintaining two complete Makefiles, reuse the coreboot build system rules in the stand-alone Makefile. Change-Id: I5d894a1f079799478bce0bd200ac735097f3806b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59669 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/ifdtool/Makefile 1 file changed, 8 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index 473dc08..83d19b8 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -2,43 +2,26 @@ # # SPDX-License-Identifier: GPL-2.0-only -PROGRAM = ifdtool - CC ?= gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror -CFLAGS += -I../../src/commonlib/include -I../../src/commonlib/bsd/include -CFLAGS += -I../cbfstool/flashmap -CFLAGS += -include ../../src/commonlib/bsd/include/commonlib/bsd/compiler.h -CFLAGS += -D_DEFAULT_SOURCE # for endianness converting functions -LDFLAGS = -OBJS = ifdtool.o -OBJS += fmap.o -OBJS += kv_pair.o -OBJS += valstr.o +HOSTCC ?= $(CC) +HOSTCFLAGS ?= $(CFLAGS) +top := ../.. +objutil := .. +include Makefile.inc -all: dep $(PROGRAM) +PROGRAM=$(objutil)/ifdtool/ifdtool -$(PROGRAM): $(OBJS) - $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) +all: $(PROGRAM) clean: rm -f $(PROGRAM) *.o *~ .dependencies distclean: clean -dep: - @$(CC) $(CFLAGS) -MM *.c > .dependencies - -%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< - -%.o: ../cbfstool/flashmap/%.c - $(CC) $(CFLAGS) -c -o $@ $< - install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/bin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin -.PHONY: all clean distclean dep +.PHONY: all clean distclean install -- To view, visit https://review.coreboot.org/c/coreboot/+/59669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d894a1f079799478bce0bd200ac735097f3806b Gerrit-Change-Number: 59669 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/intel/txt: Allow to set TXT BIOS Data Region version
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59513 ) Change subject: security/intel/txt: Allow to set TXT BIOS Data Region version ...................................................................... security/intel/txt: Allow to set TXT BIOS Data Region version TXT BIOS Data region version is checked by Trusted Boot code. Older versions of TBoot (e.g. 1.8.2) may refuse to set up the MLE if BDR version is not known. Provide an option to set the BDR version in case an older TBoot code is used. This is very useful for platforms with TPM 1.2. TEST=Set BDR version to 4 and successfully boot QubesOS 4.0 with TBoot 1.8.2 on Dell OptiPlex 9010 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ic2550bd4008559bd47de9e35f8b1c7b52e6e0f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59513 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/intel/txt/Kconfig M src/security/intel/txt/ramstage.c 2 files changed, 13 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 3648925..6d23583 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -39,6 +39,18 @@ the MRC does not have an input to specify the size of DPR, so this field is only used to check if the programmed size is large enough. +config INTEL_TXT_BDR_VERSION + int "BIOS Data Region version" + range 2 6 + default 5 if TPM1 + default 6 if TPM2 + help + Specify the TXT heap BIOS Data Region version. Sometimes when using + an older Trusted Boot version, it may report unsupported BIOS Data + Region version and refuse to set up the measured launch environment. + Setting lower version may work around such issue. Allowed values + currently range from 2 to 6. + config INTEL_TXT_TEST_BIOS_ACM_CALLING_CODE bool "Test BIOS ACM calling code with NOP function" help diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 3ca766e..217d50c 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -215,10 +215,7 @@ } __packed data = {0}; /* TPM2.0 requires version 6 of BDT */ - if (CONFIG(TPM2)) - data.bdr.version = 6; - else - data.bdr.version = 5; + data.bdr.version = CONFIG_INTEL_TXT_BDR_VERSION; data.bdr.no_logical_procs = dev_count_cpu(); -- To view, visit https://review.coreboot.org/c/coreboot/+/59513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2550bd4008559bd47de9e35f8b1c7b52e6e0f5f Gerrit-Change-Number: 59513 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/sandybridge: Add support for DPR
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59512 ) Change subject: nb/intel/sandybridge: Add support for DPR ...................................................................... nb/intel/sandybridge: Add support for DPR Include DPR in the memory map calculations if enabled. DPR is required for Intel TXT support. TEST=Boot Debian 10 and see the DPR memory being reserved in E820 and cbmem logs: "BIOS-e820: [mem 0x000000007fc09000-0x00000000829fffff] reserved" "TSEG base 0x80000000 size 8M" "DPR base 0x7fd00000 size 3M" Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59512 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c 2 files changed, 43 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 7f46d66..f667544 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -10,6 +10,7 @@ #include <cpu/x86/smm.h> #include <program_loading.h> #include "sandybridge.h" +#include <security/intel/txt/txt_platform.h> #include <stddef.h> #include <stdint.h> @@ -24,12 +25,38 @@ return CONFIG_SMM_TSEG_SIZE; } +union dpr_register txt_get_chipset_dpr(void) +{ + return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) }; +} + +/* + * Return the topmost memory address below 4 GiB available for general + * use, from software's view of memory. Do not confuse this with TOLUD, + * which applies to the DRAM as viewed by the memory controller itself. + */ +static uintptr_t top_of_low_usable_memory(void) +{ + /* + * Base of DPR is top of usable DRAM below 4 GiB. However, DPR + * may not always be enabled. Unlike most memory map registers, + * the DPR register stores top of DPR instead of its base address. + * Top of DPR is R/O, and mirrored from TSEG base by hardware. + */ + uintptr_t tolum = northbridge_get_tseg_base(); + + const union dpr_register dpr = txt_get_chipset_dpr(); + + /* Subtract DMA Protected Range size if enabled */ + if (dpr.epm) + tolum -= dpr.size * MiB; + + return tolum; +} + void *cbmem_top_chipset(void) { - /* If DPR is disabled, base of TSEG is top of usable DRAM */ - uintptr_t top_of_ram = northbridge_get_tseg_base(); - - return (void *)top_of_ram; + return (void *)top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index bd4d107..f04c4f5 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -14,6 +14,7 @@ #include "chip.h" #include "sandybridge.h" #include <cpu/intel/smm_reloc.h> +#include <security/intel/txt/txt_platform.h> /* IGD UMA memory */ static uint64_t uma_memory_base = 0; @@ -85,9 +86,11 @@ { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; + uint32_t dpr_base_k, dpr_size_k; uint16_t ggc; unsigned long long tomk; unsigned long index = 3; + const union dpr_register dpr = txt_get_chipset_dpr(); pci_dev_read_resources(dev); @@ -184,6 +187,15 @@ uma_memory_size += uma_size * 1024ULL; printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); + /* Calculate DMA Protected Region if enabled */ + if (dpr.epm && dpr.size) { + dpr_size_k = dpr.size * MiB / KiB; + tomk -= dpr_size_k; + dpr_base_k = (tseg_base - dpr.size * MiB) / KiB; + reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k); + printk(BIOS_DEBUG, "DPR base 0x%08x size %uM\n", dpr_base_k * KiB, dpr.size); + } + printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); /* Report the memory regions */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 Gerrit-Change-Number: 59512 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/medaitek/mt8186: fix wrong condition of RTC drivers
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59653 ) Change subject: soc/medaitek/mt8186: fix wrong condition of RTC drivers ...................................................................... soc/medaitek/mt8186: fix wrong condition of RTC drivers We need to report error while rtc_xosc_write() returns false. TEST=error logs for RTC disappear BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I5fdf4de0383ef373dd45e8d8741aa861c9c4bdc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59653 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/rtc.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 346fca6..7e38742 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -88,8 +88,8 @@ } rtc_read(RTC_OSC32CON, &osc32con); - if (rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | - (val & RTC_XOSCCALI_MASK))) { + if (!rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | + (val & RTC_XOSCCALI_MASK))) { rtc_info("rtc_xosc_write() failed\n"); return false; } -- To view, visit https://review.coreboot.org/c/coreboot/+/59653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fdf4de0383ef373dd45e8d8741aa861c9c4bdc6 Gerrit-Change-Number: 59653 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: Add an option for SD card initialization
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59571 ) Change subject: mb/google/corsola: Add an option for SD card initialization ...................................................................... mb/google/corsola: Add an option for SD card initialization There is no support for SD card on Corsola reference board, so we add a configuration to disable SD card initialization to prevent setting GPIOs in a mistaken way. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/mainboard.c 2 files changed, 10 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index cb6c968..b57e23b 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -30,4 +30,8 @@ config BOOT_DEVICE_SPI_FLASH_BUS int default 7 + +config SDCARD_INIT + bool + default n endif diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index 2ea81e8..d3d55a2 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -9,7 +9,12 @@ static void mainboard_init(struct device *dev) { mtk_msdc_configure_emmc(true); - mtk_msdc_configure_sdcard(); + + if (CONFIG(SDCARD_INIT)) { + printk(BIOS_INFO, "SD card init\n"); + mtk_msdc_configure_sdcard(); + } + setup_usb_host(); if (spm_init()) -- To view, visit https://review.coreboot.org/c/coreboot/+/59571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc Gerrit-Change-Number: 59571 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: Get RAM code from ADC
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59570 ) Change subject: mb/google/corsola: Get RAM code from ADC ...................................................................... mb/google/corsola: Get RAM code from ADC On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Corsola the RAM code can be read from ADC channel 2 and 3. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Makefile.inc A src/mainboard/google/corsola/boardid.c 2 files changed, 70 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index 7995f8a..1a9a1c28 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -7,11 +7,13 @@ verstage-y += reset.c romstage-y += memlayout.ld +romstage-y += boardid.c romstage-y += chromeos.c romstage-y += regulator.c romstage-y += romstage.c ramstage-y += memlayout.ld +ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += regulator.c diff --git a/src/mainboard/google/corsola/boardid.c b/src/mainboard/google/corsola/boardid.c new file mode 100644 index 0000000..285b065 --- /dev/null +++ b/src/mainboard/google/corsola/boardid.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <boardid.h> +#include <console/console.h> +#include <soc/auxadc.h> + +/* board_id is provided by ec/google/chromeec/ec_boardid.c */ + +#define ADC_LEVELS 12 + +enum { + /* RAM IDs */ + RAM_ID_LOW_CHANNEL = 2, + RAM_ID_HIGH_CHANNEL = 3, +}; + +static const unsigned int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + [0] = 74300, + [1] = 211700, + [2] = 318800, + [3] = 428600, + [4] = 541700, + [5] = 665800, + [6] = 781400, + [7] = 900000, + [8] = 1023100, + [9] = 1137000, + [10] = 1240000, + [11] = 1342600, +}; + +static const unsigned int *adc_voltages[] = { + [RAM_ID_LOW_CHANNEL] = ram_voltages, + [RAM_ID_HIGH_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + unsigned int value = auxadc_get_voltage_uv(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const unsigned int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + + printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id); + return id; +} + +uint32_t ram_code(void) +{ + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) { + cached_ram_code = (get_adc_index(RAM_ID_HIGH_CHANNEL) << 4 | + get_adc_index(RAM_ID_LOW_CHANNEL)); + printk(BIOS_DEBUG, "RAM Code: %#02x\n", cached_ram_code); + } + + return cached_ram_code; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513 Gerrit-Change-Number: 59570 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: Raise little CPU frequency
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59569 ) Change subject: mb/google/corsola: Raise little CPU frequency ...................................................................... mb/google/corsola: Raise little CPU frequency Raise little CPU to 2GHz at romstage. TEST=check little core cpu frequency is 2GHz BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/romstage.c M src/soc/mediatek/mt8186/Makefile.inc 2 files changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c index d1e9e20..aff496b 100644 --- a/src/mainboard/google/corsola/romstage.c +++ b/src/mainboard/google/corsola/romstage.c @@ -1,11 +1,29 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <console/console.h> +#include <delay.h> #include <soc/mt6366.h> +#include <soc/pll_common.h> +#include <soc/regulator.h> #include <soc/rtc.h> +static void raise_little_cpu_freq(void) +{ + mainboard_set_regulator_vol(MTK_REGULATOR_VPROC12, 1031250); + mainboard_set_regulator_vol(MTK_REGULATOR_VSRAM_PROC12, 1118750); + udelay(200); + mt_pll_raise_little_cpu_freq(2000 * MHz); + mt_pll_raise_cci_freq(1385 * MHz); + + printk(BIOS_INFO, "Check CPU freq: %u KHz, cci: %u KHz\n", + mt_fmeter_get_freq_khz(FMETER_ABIST, 9), + mt_fmeter_get_freq_khz(FMETER_ABIST, 7)); +} + void platform_romstage_main(void) { mt6366_init(); + raise_little_cpu_freq(); rtc_boot(); } diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index b1624a3..fbde650 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c -- To view, visit https://review.coreboot.org/c/coreboot/+/59569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d Gerrit-Change-Number: 59569 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021