coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cbfs: Remove deprecated APIs
by Werner Zeh (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Christian Walter, Julius Werner. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59682 ) Change subject: cbfs: Remove deprecated APIs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Thank you for driving this topic. […] I did one additional comparison. Same code base but now with TPM_MEASURED_BOOT disabled. Looks like the immense time addon is caused by the hashing in your changed code? Timestamps upstream without TPM_MEASURED_BOOT: 39 entries total: 0:1st timestamp 36,202 11:start of bootblock 46,989 (10,787) 12:end of bootblock 73,778 (26,788) 13:starting to load romstage 73,796 (17) 14:finished loading romstage 74,858 (1,062) 1:start of romstage 75,225 (367) 970:loading FSP-M 101,660 (26,435) 2:before RAM initialization 102,602 (941) 950:calling FspMemoryInit 108,950 (6,348) 951:returning from FspMemoryInit 407,530 (298,580) 3:after RAM initialization 417,027 (9,497) 4:end of romstage 428,575 (11,547) 100:start of postcar 439,632 (11,056) 101:end of postcar 439,632 (0) 8:starting to load ramstage 439,634 (2) 15:starting LZMA decompress (ignore for x86) 439,644 (9) 16:finished LZMA decompress (ignore for x86) 475,569 (35,925) 9:finished loading ramstage 475,676 (106) 10:start of ramstage 486,026 (10,350) 17:starting LZ4 decompress (ignore for x86) 486,350 (324) 18:finished LZ4 decompress (ignore for x86) 529,279 (42,928) 30:device enumeration 541,823 (12,544) 971:loading FSP-S 548,422 (6,598) 954:calling FspSiliconInit 548,435 (12) 955:returning from FspSiliconInit 583,828 (35,393) 40:device configuration 726,938 (143,110) 956:calling FspNotify(AfterPciEnumeration) 731,768 (4,829) 957:returning from FspNotify(AfterPciEnumeration) 731,970 (202) 50:device enable 731,972 (1) 60:device initialization 743,968 (11,995) 70:device setup done 774,833 (30,864) 75:cbmem post 774,842 (8) 80:write tables 778,083 (3,241) 85:finalize chips 783,681 (5,598) 90:starting to load payload 785,359 (1,677) 958:calling FspNotify(ReadyToBoot) 3,123,687 (2,338,328) 959:returning from FspNotify(ReadyToBoot) 3,124,350 (663) 960:calling FspNotify(EndOfFirmware) 3,124,351 (0) 961:returning from FspNotify(EndOfFirmware) 3,125,237 (885) 99:selfboot jump 3,125,343 (106) Total Time: 3,089,123 Timestamps with this CL on top of upstream without TPM_MEASURED_BOOT: 39 entries total: 0:1st timestamp 36,114 11:start of bootblock 46,629 (10,514) 12:end of bootblock 72,828 (26,198) 13:starting to load romstage 72,845 (17) 14:finished loading romstage 73,892 (1,046) 1:start of romstage 74,237 (344) 970:loading FSP-M 100,694 (26,457) 2:before RAM initialization 101,702 (1,007) 950:calling FspMemoryInit 107,963 (6,261) 951:returning from FspMemoryInit 406,509 (298,545) 3:after RAM initialization 415,969 (9,460) 4:end of romstage 427,533 (11,563) 100:start of postcar 438,590 (11,056) 101:end of postcar 438,590 (0) 8:starting to load ramstage 438,592 (2) 15:starting LZMA decompress (ignore for x86) 438,657 (64) 16:finished LZMA decompress (ignore for x86) 474,701 (36,044) 9:finished loading ramstage 474,889 (187) 10:start of ramstage 485,248 (10,359) 17:starting LZ4 decompress (ignore for x86) 485,498 (250) 18:finished LZ4 decompress (ignore for x86) 528,204 (42,705) 30:device enumeration 540,189 (11,985) 971:loading FSP-S 546,787 (6,597) 954:calling FspSiliconInit 546,800 (13) 955:returning from FspSiliconInit 581,997 (35,196) 40:device configuration 716,986 (134,988) 956:calling FspNotify(AfterPciEnumeration) 721,822 (4,835) 957:returning from FspNotify(AfterPciEnumeration) 722,095 (273) 50:device enable 722,097 (1) 60:device initialization 734,086 (11,988) 70:device setup done 764,961 (30,875) 75:cbmem post 764,969 (8) 80:write tables 768,208 (3,238) 85:finalize chips 773,804 (5,595) 90:starting to load payload 775,470 (1,666) 958:calling FspNotify(ReadyToBoot) 3,110,657 (2,335,186) 959:returning from FspNotify(ReadyToBoot) 3,111,320 (662) 960:calling FspNotify(EndOfFirmware) 3,111,320 (0) 961:returning from FspNotify(EndOfFirmware) 3,112,194 (873) 99:selfboot jump 3,112,300 (106) Total Time: 3,076,164 -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 26 Nov 2021 12:30:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Remove deprecated APIs
by Werner Zeh (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Christian Walter, Julius Werner. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59682 ) Change subject: cbfs: Remove deprecated APIs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Thank you for driving this topic. I gave this CL a try on mb/siemens/mc_ehl1 and compared the timestamps with upstream. With his CL payload loading takes twice as long, no clue yet why. Here are the two timestamp logs for your reference (both logs are taken from the second power on so memory is trained in both cases). Upstream timestamps: 39 entries total: 0:1st timestamp 36,230 11:start of bootblock 46,729 (10,499) 12:end of bootblock 73,207 (26,478) 13:starting to load romstage 73,235 (27) 14:finished loading romstage 89,550 (16,315) 1:start of romstage 89,576 (26) 970:loading FSP-M 113,236 (23,660) 2:before RAM initialization 217,880 (104,643) 950:calling FspMemoryInit 224,218 (6,338) 951:returning from FspMemoryInit 488,743 (264,524) 3:after RAM initialization 497,186 (8,443) 4:end of romstage 512,655 (15,468) 100:start of postcar 523,149 (10,494) 101:end of postcar 523,150 (0) 8:starting to load ramstage 523,152 (2) 15:starting LZMA decompress (ignore for x86) 560,123 (36,970) 16:finished LZMA decompress (ignore for x86) 575,138 (15,014) 9:finished loading ramstage 575,250 (112) 10:start of ramstage 585,016 (9,765) 17:starting LZ4 decompress (ignore for x86) 633,667 (48,650) 18:finished LZ4 decompress (ignore for x86) 633,769 (102) 30:device enumeration 645,845 (12,076) 971:loading FSP-S 652,443 (6,597) 954:calling FspSiliconInit 652,457 (14) 955:returning from FspSiliconInit 687,942 (35,485) 40:device configuration 729,721 (41,778) 956:calling FspNotify(AfterPciEnumeration) 734,743 (5,022) 957:returning from FspNotify(AfterPciEnumeration) 734,988 (244) 50:device enable 734,990 (1) 60:device initialization 774,648 (39,657) 70:device setup done 805,678 (31,029) 75:cbmem post 805,686 (8) 80:write tables 808,926 (3,239) 85:finalize chips 817,528 (8,601) 90:starting to load payload 819,204 (1,676) 958:calling FspNotify(ReadyToBoot) 5,515,270 (4,696,065) 959:returning from FspNotify(ReadyToBoot) 5,515,933 (662) 960:calling FspNotify(EndOfFirmware) 5,515,933 (0) 961:returning from FspNotify(EndOfFirmware) 5,516,809 (876) 99:selfboot jump 5,517,619 (809) Total Time: 5,481,369 Timestamps with the CL on top of upstream: 39 entries total: 0:1st timestamp 36,210 11:start of bootblock 46,813 (10,603) 12:end of bootblock 73,210 (26,396) 13:starting to load romstage 73,238 (27) 14:finished loading romstage 89,679 (16,441) 1:start of romstage 89,704 (24) 970:loading FSP-M 113,193 (23,489) 2:before RAM initialization 217,926 (104,733) 950:calling FspMemoryInit 224,260 (6,333) 951:returning from FspMemoryInit 488,756 (264,496) 3:after RAM initialization 497,072 (8,316) 4:end of romstage 515,797 (18,724) 100:start of postcar 526,325 (10,528) 101:end of postcar 526,326 (0) 8:starting to load ramstage 526,365 (38) 15:starting LZMA decompress (ignore for x86) 562,052 (35,687) 16:finished LZMA decompress (ignore for x86) 576,956 (14,903) 9:finished loading ramstage 577,203 (247) 10:start of ramstage 586,998 (9,794) 17:starting LZ4 decompress (ignore for x86) 635,735 (48,736) 18:finished LZ4 decompress (ignore for x86) 635,836 (101) 30:device enumeration 647,914 (12,077) 971:loading FSP-S 654,509 (6,594) 954:calling FspSiliconInit 654,523 (14) 955:returning from FspSiliconInit 689,757 (35,234) 40:device configuration 729,707 (39,949) 956:calling FspNotify(AfterPciEnumeration) 734,987 (5,279) 957:returning from FspNotify(AfterPciEnumeration) 735,190 (203) 50:device enable 735,192 (1) 60:device initialization 775,192 (40,000) 70:device setup done 806,060 (30,868) 75:cbmem post 806,069 (8) 80:write tables 809,308 (3,239) 85:finalize chips 817,921 (8,613) 90:starting to load payload 819,607 (1,685) 958:calling FspNotify(ReadyToBoot) 10,165,818 (9,346,210) 959:returning from FspNotify(ReadyToBoot) 10,166,473 (655) 960:calling FspNotify(EndOfFirmware) 10,166,473 (0) 961:returning from FspNotify(EndOfFirmware) 10,167,349 (875) 99:selfboot jump 10,168,161 (811) Total Time: 10,131,931 -- To view, visit https://review.coreboot.org/c/coreboot/+/59682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Gerrit-Change-Number: 59682 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 26 Nov 2021 12:11:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: Configure the ISOLATE pin of LAN
by Alan Huang (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58105 ) Change subject: mb/google/brya/var/brask: Configure the ISOLATE pin of LAN ...................................................................... Patch Set 9: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58105/comment/a7605d09_c85cef4e PS6, Line 7: Configurate > Configure Done https://review.coreboot.org/c/coreboot/+/58105/comment/88cfaf68_ca17e6d5 PS6, Line 9: Copy the default configuration from Puff. : Update the 'stop_gpio' to GPP_H22. : Remove 'wake'. ("WAKE#" is not a GPIO pin.) > Please format this as a list. Done https://review.coreboot.org/c/coreboot/+/58105/comment/003eda4d_58806779 PS6, Line 15: Build Pass > Maybe note down the command. Done https://review.coreboot.org/c/coreboot/+/58105/comment/5ba1ee28_ed961077 PS6, Line 15: Pass > pass Done Patchset: PS9: Don't know why it is still 'Merge Conflict'. I have done git pull, git rebase and git push again... File src/drivers/net/r8168.c: PS5: > Separate to https://review.coreboot. […] Done File src/mainboard/google/brya/variants/brask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/58105/comment/fd243ebf_b5dd598f PS5, Line 86: register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)" > So this PowerResource will look sorta like this: […] Yes. The ISOLATE pin is active low. Tested on wake-pin reworked device and the wakeonlan function is still working. -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 9 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 26 Nov 2021 12:04:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Martin Roth, Mario Scheithauer, Werner Zeh, Felix Held. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 57: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55367/comment/a0735cb5_358e0d68 PS52, Line 129: /* Set the ownership of these devices to PSE */ : params->PchPseDmaEnable[0] = PSE_Owned; : params->PchPseUartEnable[2] = PSE_Owned; : params->PchPseHsuartEnable[2] = PSE_Owned; : params->PchPseI2cEnable[2] = PSE_Owned; : params->PchPseTimedGpioEnable[0] = PSE_Owned; : params->PchPseTimedGpioEnable[1] = PSE_Owned; : /* Disable PSE DMA Sideband Interrupt for DMA 0 */ : params->PchPseDmaSbInterruptEnable[0] = 0; : /* Set the log output to PSE UART 2 */ : params->PchPseLogOutputChannel = 3; > Yes, both alternatives are fine with me. Thanks Paul again. Done added the comments. Please help to check. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 57 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 26 Nov 2021 11:56:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by build bot (Jenkins) (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 57: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-134485): https://review.coreboot.org/c/coreboot/+/55367/comment/65b490ef_3119e91a PS57, Line 127: * trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 57 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 26 Nov 2021 11:55:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Lean Sheng Tan (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Martin Roth, Mario Scheithauer, Lean Sheng Tan, Werner Zeh, Felix Held. Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55367 to look at the new patch set (#57). Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... soc/intel/elkhartlake: Introduce Intel PSE The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and its peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate the PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate the PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enable the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/romstage/fsp_params.c 5 files changed, 174 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/57 -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 57 Gerrit-Owner: Lean Sheng Tan Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: David Wu, Paul Menzel, Tim Wawrzynczak, Zhuohao Lee. Hello build bot (Jenkins), David Wu, Paul Menzel, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59086 to look at the new patch set (#13). Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... drivers/net/r8168: Add support for Realtek RT8125 The Realtek RT8168 and RT8125 have a similar programming interface, therefore add the PCI device ID for the RT8125 into driver for support. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC is RT8125. Check if the default MAC is written into the NIC. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 --- M src/drivers/net/r8168.c M src/include/device/pci_ids.h 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 13 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/brask: Configure the ISOLATE pin of LAN
by Alan Huang (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: David Wu, Zhuohao Lee. Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58105 to look at the new patch set (#8). Change subject: mb/google/brya/var/brask: Configure the ISOLATE pin of LAN ...................................................................... mb/google/brya/var/brask: Configure the ISOLATE pin of LAN 1. Copy the default configuration from Puff. 2. Update the 'stop_gpio' to GPP_H22. BUG=b:193750191 BRANCH=None TEST=Update kernel for 8125 outbox driver and test with command suspend_stress_test. Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/58105/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 8 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/brask: Enable LAN driver to write MAC
by Alan Huang (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59087 ) Change subject: mb/google/brya/var/brask: Enable LAN driver to write MAC ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Fixed the merge conflict. -- To view, visit https://review.coreboot.org/c/coreboot/+/59087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732 Gerrit-Change-Number: 59087 Gerrit-PatchSet: 2 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 26 Nov 2021 11:32:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/i2c: Return negative values on error
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59539 ) Change subject: soc/mediatek/i2c: Return negative values on error ...................................................................... soc/mediatek/i2c: Return negative values on error Following coreboot's convention, return negative error codes from platform_i2c_transfer(). BUG=none TEST=emerge-asurada coreboot BRANCH=none Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59539 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h 2 files changed, 18 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index b9b02cd..c47e08e 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -106,10 +106,10 @@ mtk_i2c_dump_more_info(regs); } -static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, - enum i2c_modes mode) +static int mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, + enum i2c_modes mode) { - uint32_t ret_code = I2C_OK; + int ret = I2C_OK; uint16_t status; uint16_t dma_sync = 0; uint32_t time_out_val = 0; @@ -245,23 +245,23 @@ while (1) { status = read32(&regs->intr_stat); if (status & I2C_HS_NACKERR) { - ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; + ret = I2C_TRANSFER_FAIL_HS_NACKERR; printk(BIOS_ERR, "[i2c%d] transfer NACK error\n", bus); mtk_i2c_dump_info(regs); break; } else if (status & I2C_ACKERR) { - ret_code = I2C_TRANSFER_FAIL_ACKERR; + ret = I2C_TRANSFER_FAIL_ACKERR; printk(BIOS_ERR, "[i2c%d] transfer ACK error\n", bus); mtk_i2c_dump_info(regs); break; } else if (status & I2C_TRANSAC_COMP) { - ret_code = I2C_OK; + ret = I2C_OK; memcpy(read_buffer, _dma_coherent, read_len); break; } if (stopwatch_expired(&sw)) { - ret_code = I2C_TRANSFER_FAIL_TIMEOUT; + ret = I2C_TRANSFER_FAIL_TIMEOUT; printk(BIOS_ERR, "[i2c%d] transfer timeout:%d\n", bus, time_out_val); mtk_i2c_dump_info(regs); @@ -279,7 +279,7 @@ /* reset the i2c controller for next i2c transfer. */ i2c_hw_reset(bus); - return ret_code; + return ret; } static bool mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) @@ -301,7 +301,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int seg_count) { - int ret = 0; + int ret; int i; int mode; @@ -314,15 +314,14 @@ } ret = mtk_i2c_transfer(bus, &segments[i], mode); - - if (ret) - break; + if (ret < 0) + return ret; if (mode == I2C_WRITE_READ_MODE) i++; } - return ret; + return 0; } /* diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 7df1ac5..4f4449c 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -88,12 +88,12 @@ /* I2C Status Code */ enum { I2C_OK = 0x0000, - I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, - I2C_TRANSFER_INVALID_LENGTH = 0xA002, - I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, - I2C_TRANSFER_FAIL_ACKERR = 0xA004, - I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, - I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 + I2C_SET_SPEED_FAIL_OVER_SPEED = -0xA001, + I2C_TRANSFER_INVALID_LENGTH = -0xA002, + I2C_TRANSFER_FAIL_HS_NACKERR = -0xA003, + I2C_TRANSFER_FAIL_ACKERR = -0xA004, + I2C_TRANSFER_FAIL_TIMEOUT = -0xA005, + I2C_TRANSFER_INVALID_ARGUMENT = -0xA006, }; struct mtk_i2c_ac_timing { -- To view, visit https://review.coreboot.org/c/coreboot/+/59539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Gerrit-Change-Number: 59539 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wei-Shun Chang <weishunc(a)google.com> Gerrit-Reviewer: Xin Ji <xji(a)analogix.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021