coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interface
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59568 ) Change subject: mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interface ...................................................................... mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interface Add VPROC12/VSRAM_PROC12 to adjust power for raising little CPU frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I59b4627220022a51a116716036a8ba0048039508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/regulator.c M src/soc/mediatek/common/include/soc/regulator.h 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/regulator.c b/src/mainboard/google/corsola/regulator.c index b1310af..1dd26d3 100644 --- a/src/mainboard/google/corsola/regulator.c +++ b/src/mainboard/google/corsola/regulator.c @@ -18,6 +18,8 @@ [MTK_REGULATOR_VDRAM1] = MT6366_VDRAM1, [MTK_REGULATOR_VMCH] = MT6366_VMCH, [MTK_REGULATOR_VMC] = MT6366_VMC, + [MTK_REGULATOR_VPROC12] = MT6366_VPROC12, + [MTK_REGULATOR_VSRAM_PROC12] = MT6366_VSRAM_PROC12, }; _Static_assert(ARRAY_SIZE(regulator_id) == MTK_REGULATOR_NUM, "regulator_id size error"); diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h index a53d01c..5068f50 100644 --- a/src/soc/mediatek/common/include/soc/regulator.h +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -16,6 +16,8 @@ MTK_REGULATOR_VDRAM1, MTK_REGULATOR_VMCH, MTK_REGULATOR_VMC, + MTK_REGULATOR_VPROC12, + MTK_REGULATOR_VSRAM_PROC12, MTK_REGULATOR_NUM, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59b4627220022a51a116716036a8ba0048039508 Gerrit-Change-Number: 59568 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: fix variable type
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59567 ) Change subject: soc/mediatek/mt8186: fix variable type ...................................................................... soc/mediatek/mt8186: fix variable type The types of pwrap_read_field()'s return value and pwrap_write_field()'s `val` argument are u16, so correct the usage in MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ie05ab65ecd9b8ea1379ef74393285c4f5d2db8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59567 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/mt6366.c 1 file changed, 13 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 406c524..450b783 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -473,7 +473,7 @@ static u32 pmic_get_vcore_vol(void) { - u32 vol_reg; + u16 vol_reg; vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0); return 500000 + vol_reg * 6250; @@ -481,7 +481,7 @@ static void pmic_set_vcore_vol(u32 vcore_uv) { - u32 vol_reg; + u16 vol_reg; assert(vcore_uv >= 500000); assert(vcore_uv <= 1100000); @@ -539,7 +539,7 @@ static u32 pmic_get_vdram1_vol(void) { - u32 vol_reg; + u16 vol_reg; vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); return 500000 + vol_reg * 12500; @@ -547,7 +547,7 @@ static void pmic_set_vdram1_vol(u32 vdram_uv) { - u32 vol_reg; + u16 vol_reg; assert(vdram_uv >= 500000); assert(vdram_uv <= 1300000); @@ -562,7 +562,7 @@ static u32 pmic_get_vddq_vol(void) { int efuse_votrim; - u32 cali_trim; + u16 cali_trim; if (!pwrap_read_field(PMIC_VDDQ_OP_EN, 0x1, 15)) return 0; @@ -575,7 +575,8 @@ static void pmic_set_vddq_vol(u32 vddq_uv) { - int target_mv, dram2_ori_mv, cali_offset_uv, cali_trim; + int target_mv, dram2_ori_mv, cali_offset_uv; + u16 cali_trim; assert(vddq_uv >= 530000); assert(vddq_uv <= 680000); @@ -606,7 +607,8 @@ static u32 pmic_get_vmch_vol(void) { - u32 vol_reg, ret; + u32 ret; + u16 vol_reg; vol_reg = pwrap_read_field(PMIC_VMCH_ANA_CON0, 0x7, 8); @@ -630,7 +632,7 @@ static void pmic_set_vmch_vol(u32 vmch_uv) { - u32 val = 0; + u16 val = 0; switch (vmch_uv) { case 2900000: @@ -656,7 +658,8 @@ static u32 pmic_get_vmc_vol(void) { - u32 vol_reg, ret; + u32 ret; + u16 vol_reg; vol_reg = pwrap_read_field(PMIC_VMC_ANA_CON0, 0xF, 8); @@ -683,7 +686,7 @@ static void pmic_set_vmc_vol(u32 vmc_uv) { - u32 val = 0; + u16 val = 0; switch (vmc_uv) { case 1800000: -- To view, visit https://review.coreboot.org/c/coreboot/+/59567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05ab65ecd9b8ea1379ef74393285c4f5d2db8a4 Gerrit-Change-Number: 59567 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59566 ) Change subject: soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12 ...................................................................... soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12 To raise little CPU frequency, add support for VPROC12 and VSRAM_PROC12 of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo(a)mediatek.corp-partner.google.com> Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59566 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/include/soc/mt6366.h M src/soc/mediatek/mt8186/mt6366.c 2 files changed, 62 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/include/soc/mt6366.h b/src/soc/mediatek/mt8186/include/soc/mt6366.h index 76fcf54..af77da2 100644 --- a/src/soc/mediatek/mt8186/include/soc/mt6366.h +++ b/src/soc/mediatek/mt8186/include/soc/mt6366.h @@ -28,6 +28,9 @@ PMIC_TOP_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, + PMIC_VPROC12_OP_EN = 0x1410, + PMIC_VPROC12_DBG0 = 0x141e, + PMIC_VPROC12_VOSEL = 0x1426, PMIC_VCORE_OP_EN = 0x1490, PMIC_VCORE_DBG0 = 0x149e, PMIC_VCORE_VOSEL = 0x14aa, @@ -37,6 +40,9 @@ PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, PMIC_VDDQ_OP_EN = 0x1b16, + PMIC_VSRAM_PROC12_OP_EN = 0x1b90, + PMIC_VSRAM_PROC12_DBG0 = 0x1ba2, + PMIC_VSRAM_PROC12_VOSEL = 0x1bf0, PMIC_LDO_VMC_CON0 = 0x1cc4, PMIC_LDO_VMC_OP_EN = 0x1cc6, PMIC_LDO_VMCH_CON0 = 0x1cd8, @@ -53,6 +59,8 @@ MT6366_VDDQ, MT6366_VMCH, MT6366_VMC, + MT6366_VPROC12, + MT6366_VSRAM_PROC12, MT6366_REGULATOR_NUM, }; diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index e63a264..406c524 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -493,6 +493,50 @@ udelay(1); } +static u32 pmic_get_vproc12_vol(void) +{ + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VPROC12_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +static void pmic_set_vproc12_vol(u32 v_uv) +{ + u16 vol_reg; + + assert(v_uv >= 500000); + assert(v_uv <= 1293750); + + vol_reg = (v_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VPROC12_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VPROC12_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +static u32 pmic_get_vsram_proc12_vol(void) +{ + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VSRAM_PROC12_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +static void pmic_set_vsram_proc12_vol(u32 v_uv) +{ + u16 vol_reg; + + assert(v_uv >= 500000); + assert(v_uv <= 1293750); + + vol_reg = (v_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VSRAM_PROC12_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VSRAM_PROC12_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + static u32 pmic_get_vdram1_vol(void) { u32 vol_reg; @@ -779,6 +823,12 @@ case MT6366_VMC: pmic_set_vmc_vol(voltage_uv); break; + case MT6366_VPROC12: + pmic_set_vproc12_vol(voltage_uv); + break; + case MT6366_VSRAM_PROC12: + pmic_set_vsram_proc12_vol(voltage_uv); + break; default: printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); break; @@ -798,6 +848,10 @@ return pmic_get_vmch_vol(); case MT6366_VMC: return pmic_get_vmc_vol(); + case MT6366_VPROC12: + return pmic_get_vproc12_vol(); + case MT6366_VSRAM_PROC12: + return pmic_get_vsram_proc12_vol(); default: printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/59566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904 Gerrit-Change-Number: 59566 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/corsola: configure GPIOs
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59565 ) Change subject: mb/google/corsola: configure GPIOs ...................................................................... mb/google/corsola: configure GPIOs Configure Chromebook specific GPIOs, including EC_AP_INT, EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/bootblock.c M src/mainboard/google/corsola/chromeos.c A src/mainboard/google/corsola/gpio.h 3 files changed, 42 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c index e9ae5ce..bb76b98 100644 --- a/src/mainboard/google/corsola/bootblock.c +++ b/src/mainboard/google/corsola/bootblock.c @@ -4,7 +4,10 @@ #include <device/mmio.h> #include <soc/spi.h> +#include "gpio.h" + void bootblock_mainboard_init(void) { mtk_snfc_init(SPI_NOR_GPIO_SET0); + setup_chromeos_gpios(); } diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c index 3f0937f..6a727c9 100644 --- a/src/mainboard/google/corsola/chromeos.c +++ b/src/mainboard/google/corsola/chromeos.c @@ -2,10 +2,29 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <gpio.h> + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_GSC_AP_INT); + gpio_output(GPIO_EN_SPK, 0); + gpio_output(GPIO_RESET, 0); +} void fill_lb_gpios(struct lb_gpios *gpios) { - + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"}, + {GPIO_GSC_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/corsola/gpio.h b/src/mainboard/google/corsola/gpio.h new file mode 100644 index 0000000..78dd252 --- /dev/null +++ b/src/mainboard/google/corsola/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_CORSOLA_GPIO_H__ +#define __MAINBOARD_GOOGLE_CORSOLA_GPIO_H__ + +#include <soc/gpio.h> + +#define GPIO_EC_AP_INT GPIO(EINT13) +#define GPIO_WP GPIO(EINT16) +#define GPIO_BEEP_ON GPIO(PERIPHERAL_EN4) +#define GPIO_XHCI_DONE GPIO(PERIPHERAL_EN1) +#define GPIO_EC_IN_RW GPIO(EINT14) +#define GPIO_GSC_AP_INT GPIO(EINT15) +#define GPIO_EN_SPK GPIO(PERIPHERAL_EN3) +#define GPIO_RESET GPIO(PERIPHERAL_EN0) + +void setup_chromeos_gpios(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1 Gerrit-Change-Number: 59565 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: Support 5 temperature sensors
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59633 ) Change subject: ec/google/chromeec: Support 5 temperature sensors ...................................................................... ec/google/chromeec: Support 5 temperature sensors Some boards with the chrome EC will need to support more than 4 temperature sensors, so modify the number of TSRs supported when generating the ACPI code. Note that the EC memory map already has support for up to 16 TSRs, so no change is required on the EC side. BUG=b:207585491 TEST=with previous patch and some test data in brya0 overridetree.cb, dump the SSDT and verify that all of the existing Methods for TSR0-TSR3 are also added for TSR4, as well as all Notify, etc. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59633 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec_dptf_helpers.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, approved Scott Chao: Looks good to me, but someone else must approve diff --git a/src/ec/google/chromeec/ec_dptf_helpers.c b/src/ec/google/chromeec/ec_dptf_helpers.c index 631f16e..94b13fb 100644 --- a/src/ec/google/chromeec/ec_dptf_helpers.c +++ b/src/ec/google/chromeec/ec_dptf_helpers.c @@ -265,7 +265,7 @@ /* Local0 = ToInteger(Arg0) */ acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { snprintf(name, sizeof(name), "^TSR%1d", i); acpigen_write_if_lequal_op_int(LOCAL0_OP, i); acpigen_notify(name, THERMAL_EVENT); @@ -277,7 +277,7 @@ /* TPET */ acpigen_write_method("TPET", 0); - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { snprintf(name, sizeof(name), "^TSR%1d", i); acpigen_notify(name, TRIP_POINTS_CHANGED_EVENT); } @@ -355,6 +355,6 @@ write_charger_methods(ec); write_fan_methods(ec); - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) write_thermal_methods(ec, p, i); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d Gerrit-Change-Number: 59633 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: dptf: Add support for one more temperature sensor
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59632 ) Change subject: dptf: Add support for one more temperature sensor ...................................................................... dptf: Add support for one more temperature sensor Some boards may use more than 4 temperature sensors for DPTF thermal control, so this patch adds support for one more temperature sensor. BUG=b:207585491 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59632 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 3 files changed, 6 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, approved Scott Chao: Looks good to me, but someone else must approve diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index ea1efcf..f2ae769 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -70,6 +70,8 @@ return "TSR2"; case DPTF_TEMP_SENSOR_3: return "TSR3"; + case DPTF_TEMP_SENSOR_4: + return "TSR4"; case DPTF_TPCH: return "TPCH"; default: diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index c6ead0f..71a25b6 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -192,7 +192,7 @@ get_STA_value(config, DPTF_CHARGER), platform_info); - for (i = 0, participant = DPTF_TEMP_SENSOR_0; i < 4; ++i, ++participant) { + for (i = 0, participant = DPTF_TEMP_SENSOR_0; i < DPTF_MAX_TSR; ++i, ++participant) { snprintf(name, sizeof(name), "TSR%1d", i); dptf_write_generic_participant(name, DPTF_GENERIC_PARTICIPANT_TYPE_TSR, NULL, get_STA_value(config, participant), @@ -449,7 +449,7 @@ acpigen_pop_len(); /* Scope */ /* TSR options */ - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { if (is_participant_used(config, p) && (config->options.tsr[i].hysteresis || config->options.tsr[i].desc)) { dptf_write_scope(p); diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index de57adc..758398d 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -24,6 +24,7 @@ DPTF_TEMP_SENSOR_1, DPTF_TEMP_SENSOR_2, DPTF_TEMP_SENSOR_3, + DPTF_TEMP_SENSOR_4, DPTF_TPCH, DPTF_PARTICIPANT_COUNT, }; @@ -44,7 +45,7 @@ DPTF_FIELD_UNUSED = 0xFFFFFFFFull, /* Max supported by DPTF */ - DPTF_MAX_TSR = 4, + DPTF_MAX_TSR = 5, }; /* Active Policy */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45 Gerrit-Change-Number: 59632 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kano: swap TPM i2c with TS i2c for the next build ...
by Felix Held (Code Review) 26 Nov '21

26 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59560 ) Change subject: mb/google/brya/var/kano: swap TPM i2c with TS i2c for the next build phase ...................................................................... mb/google/brya/var/kano: swap TPM i2c with TS i2c for the next build phase Kano EVT will exchange i2c port for touchscreen and cr50. BUG=b:195853169 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59560 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/kano/overridetree.cb 3 files changed, 68 insertions(+), 43 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1b4f6ae..6231762 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -72,7 +72,16 @@ config DRIVER_TPM_I2C_BUS hex - default 0x3 + default 0x3 if BOARD_GOOGLE_BRYA0 + default 0x3 if BOARD_GOOGLE_BRASK + default 0x3 if BOARD_GOOGLE_PRIMUS + default 0x3 if BOARD_GOOGLE_GIMBLE + default 0x3 if BOARD_GOOGLE_REDRIX + default 0x1 if BOARD_GOOGLE_KANO + default 0x3 if BOARD_GOOGLE_TAEKO + default 0x3 if BOARD_GOOGLE_FELWINTER + default 0x3 if BOARD_GOOGLE_ANAHERA + default 0x3 if BOARD_GOOGLE_VELL config DRIVER_TPM_I2C_ADDR hex diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 818ddd0..d77abea 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -108,10 +108,6 @@ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -133,6 +129,10 @@ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 56dfc6f..e0ac351 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -36,14 +36,30 @@ #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | SAR0 | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C2 | SAR0 | + #| I2C3 | Touchscreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -232,37 +248,10 @@ end end #I2C0 device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN90FC"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" - register "generic.reset_off_delay_ms" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "6" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end - end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - # GPP_D6 is the IRQ source, and GPP_D17 is the wake source - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)" - register "key.wake_gpe" = "GPE0_DW1_17" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end end end device ref i2c2 on @@ -421,10 +410,37 @@ end end device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_D6 is the IRQ source, and GPP_D17 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)" + register "key.wake_gpe" = "GPE0_DW1_17" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end end end device ref i2c5 on 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465 Gerrit-Change-Number: 59560 Gerrit-PatchSet: 6 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ChromeOS: Refactor ACPI CNVS generation
by Kyösti Mälkki (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: Lance Zhao, Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55502 ) Change subject: ChromeOS: Refactor ACPI CNVS generation ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: > just assumptions about the paths involved, snippets from dmesg: > > > ``` > [ 0.197888] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW], AE_NOT_FOUND (20200925/dswload2-163) Hmm.. Did I move CRHW, I don't think so. ACPI specs says all device objects should be under \_SB though? > [ 0.197895] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20200925/psobject-220) > [ 0.197928] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.CNVS], AE_NOT_FOUND (20200925/dsfield-501) This I did move. I will put it back to \CNVS if it makes this commit work. > looks like it breaks chromeos-ramoops as well Did it break other than ramoops.asl? -- To view, visit https://review.coreboot.org/c/coreboot/+/55502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Gerrit-Change-Number: 55502 Gerrit-PatchSet: 15 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 26 Nov 2021 11:15:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: David Wu, Paul Menzel, Tim Wawrzynczak, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59086 ) Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... Patch Set 12: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59086/comment/8086e2be_f5abcc79 PS2, Line 7: mb/google/brya/var/brask: Make LAN driver to support RT8125 > Ack Done https://review.coreboot.org/c/coreboot/+/59086/comment/05ff9672_548f211b PS2, Line 8: : Add new device id 0x8125 to the driver. > Ack Done Commit Message: https://review.coreboot.org/c/coreboot/+/59086/comment/3d296b5c_247a2b91 PS7, Line 9: The Realtek RT8168 and RT8125 have a similar programming : interface, therefore add the PCI device ID for the RT8125 : into driver for support. > Fixed. Done https://review.coreboot.org/c/coreboot/+/59086/comment/24babf17_2dc89f5b PS7, Line 14: TEST=emerge-brask coreboot chromeos-bootimage > Added the testing detail in the message. Done File src/drivers/net/r8168.c: https://review.coreboot.org/c/coreboot/+/59086/comment/29a7d2b0_d7f39710 PS2, Line 364: 0x8168, : 0x8125, > Ack Done https://review.coreboot.org/c/coreboot/+/59086/comment/174988d0_22aa5d57 PS2, Line 371: 0x10ec > Ack Done File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/59086/comment/5f4900ae_05a44444 PS7, Line 1287: #define PCI_DEVICE_ID_REALTEK_8125 0x8125 > Sorted. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 12 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 26 Nov 2021 11:01:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: Set PL and PsysPL
by Alan Huang (Code Review) 26 Nov '21

26 Nov '21

Attention is currently required from: David Wu, Hou-hsun Lee, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59576 ) Change subject: mb/google/brya/var/brask: Set PL and PsysPL ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/brya/variants/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/59576/comment/316594ce_78f20a48 PS1, Line 18: { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 5000, 45000, 80000, 80000, 159000 }, > Those PL2/PL4 values look like coming from baseline config. […] According to the HW design, we will use performance config. From doc#626774, 482 28W SKU which maps to PCI_DEVICE_ID_INTEL_ADL_P_ID_5 also has a new PL4 value 90W, right? Thanks. https://review.coreboot.org/c/coreboot/+/59576/comment/5ebca809_295c96f4 PS1, Line 23: { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135, 257 }, > If the psys_pmax_power is not used at all, I think it's better to remove it to avoid confusion. […] Yes. psys_pmax is calculated by psys_imax_ma * volts_mv. Removed psys_pmax from the structure. -- To view, visit https://review.coreboot.org/c/coreboot/+/59576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Gerrit-Change-Number: 59576 Gerrit-PatchSet: 2 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 26 Nov 2021 10:52:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-MessageType: comment

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