coreboot-gerrit October 2021

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Change in coreboot[master]: lib/thread: Remove thread stack alignment requirement
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57928 ) Change subject: lib/thread: Remove thread stack alignment requirement ...................................................................... lib/thread: Remove thread stack alignment requirement CPU_INFO_V2 now encapsulates the cpu_info requirements. They no longer need to leak through to thread.c. This allows us to remove the alignment requirement. BUG=b:179699789 TEST=Reboot stress test guybrush 50 times. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef Reviewed-on: https://review.coreboot.org/c/coreboot/+/57928 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Peers <epeers(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/lib/thread.c 1 file changed, 5 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Peers: Looks good to me, but someone else must approve diff --git a/src/lib/thread.c b/src/lib/thread.c index ac8460c..9008147e 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -11,16 +11,7 @@ #include <thread.h> #include <timer.h> -/* Can't use the IS_POWER_OF_2 in _Static_assert */ -_Static_assert((CONFIG_STACK_SIZE & (CONFIG_STACK_SIZE - 1)) == 0, - "`cpu_info()` requires the stack size to be a power of 2"); - -/* - * struct cpu_info lives at the top of each thread's stack. `cpu_info()` locates this struct by - * taking the current stack pointer and masking off CONFIG_STACK_SIZE. This requires the stack - * to be STACK_SIZE aligned. - */ -static u8 thread_stacks[CONFIG_STACK_SIZE * CONFIG_NUM_THREADS] __aligned(CONFIG_STACK_SIZE); +static u8 thread_stacks[CONFIG_STACK_SIZE * CONFIG_NUM_THREADS] __aligned(sizeof(uint64_t)); static bool initialized; static void idle_thread_init(void); @@ -90,6 +81,9 @@ t = pop_thread(&free_threads); /* Reset the current stack value to the original. */ + if (!t->stack_orig) + die("%s: Invalid stack value\n", __func__); + t->stack_current = t->stack_orig; return t; @@ -250,15 +244,10 @@ if (initialized) return; - /* `cpu_info()` requires the stacks to be STACK_SIZE aligned */ - assert(IS_ALIGNED((uintptr_t)thread_stacks, CONFIG_STACK_SIZE)); - - /* Initialize the BSP thread first. The cpu_info structure is assumed - * to be just under the top of the stack. */ t = &all_threads[0]; ci = cpu_info(); ci->thread = t; - t->stack_orig = (uintptr_t)ci; + t->stack_orig = (uintptr_t)NULL; /* We never free the main thread */ t->id = 0; t->can_yield = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/57928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef Gerrit-Change-Number: 57928 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: deduplicate acpi_fill_soc_wake
by Michael Niewöhner (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Duncan Laurie, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58043 ) Change subject: soc/intel: deduplicate acpi_fill_soc_wake ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/58043/comment/11653c89_3e0ad8f8 PS1, Line 220: RTC_EN > > I guess, if this power-well oddity exists at all, the correct way to deal […] RTC_EN confirmed too now (was my fault...) -- To view, visit https://review.coreboot.org/c/coreboot/+/58043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Gerrit-Change-Number: 58043 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Duncan Laurie Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 05 Oct 2021 22:39:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "soc/amd/cezanne: Disable Co-op multitasking"
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57894 ) Change subject: Revert "soc/amd/cezanne: Disable Co-op multitasking" ...................................................................... Revert "soc/amd/cezanne: Disable Co-op multitasking" This reverts commit 5f80e7c764b9a1cb46beeaa490a4f60be04abcd4. The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2 into this patch to satisfy the dependency. BUG=b:194391185, b:179699789 TEST=reboot stress test guybrush for 50 iterations. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Peers <epeers(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Peers: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 487b9f5..ae2f61f 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -16,8 +16,10 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select CPU_INFO_V2 select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE + select COOP_MULTITASKING select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA @@ -30,6 +32,7 @@ select IDT_IN_EVERY_STAGE select IOAPIC select PARALLEL_MP_AP_WORK + select PAYLOAD_PRELOAD select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/57894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea Gerrit-Change-Number: 57894 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/thread: Switch to using CPU_INFO_V2
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57628 ) Change subject: lib/thread: Switch to using CPU_INFO_V2 ...................................................................... lib/thread: Switch to using CPU_INFO_V2 CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1 cpu_info struct per cpu. This means that we no longer need to allocate it at the top of each threads stack. We can now in theory remove the CONFIG_STACK_SIZE alignment on the thread stack sizes. We can also in theory use threads in SMM if you are feeling venturesome. BUG=b:194391185, b:179699789 TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Peers <epeers(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/Kconfig M src/lib/thread.c 2 files changed, 6 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Peers: Looks good to me, but someone else must approve diff --git a/src/Kconfig b/src/Kconfig index 09bc22d..ea05215 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -677,7 +677,7 @@ config COOP_MULTITASKING def_bool n - depends on TIMER_QUEUE && ARCH_X86 + depends on TIMER_QUEUE && ARCH_X86 && CPU_INFO_V2 help Cooperative multitasking allows callbacks to be multiplexed on the main thread of ramstage. With this enabled it allows for multiple diff --git a/src/lib/thread.c b/src/lib/thread.c index 2ff09a5..ac8460c 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -36,28 +36,17 @@ static struct thread *runnable_threads; static struct thread *free_threads; -static inline struct cpu_info *thread_cpu_info(const struct thread *t) -{ - return (void *)(t->stack_orig); -} - static inline int thread_can_yield(const struct thread *t) { return (t != NULL && t->can_yield > 0); } -/* Assumes current CPU info can switch. */ -static inline struct thread *cpu_info_to_thread(const struct cpu_info *ci) -{ - return ci->thread; -} - static inline struct thread *current_thread(void) { if (!initialized) return NULL; - return cpu_info_to_thread(cpu_info()); + return cpu_info()->thread; } static inline int thread_list_empty(struct thread **list) @@ -94,21 +83,12 @@ static inline struct thread *get_free_thread(void) { struct thread *t; - struct cpu_info *ci; - struct cpu_info *new_ci; if (thread_list_empty(&free_threads)) return NULL; t = pop_thread(&free_threads); - ci = cpu_info(); - - /* Initialize the cpu_info structure on the new stack. */ - new_ci = thread_cpu_info(t); - *new_ci = *ci; - new_ci->thread = t; - /* Reset the current stack value to the original. */ t->stack_current = t->stack_orig; @@ -134,6 +114,7 @@ static void schedule(struct thread *t) { struct thread *current = current_thread(); + struct cpu_info *ci = cpu_info(); /* If t is NULL need to find new runnable thread. */ if (t == NULL) { @@ -148,6 +129,8 @@ if (t->handle) t->handle->state = THREAD_STARTED; + ci->thread = t; + switch_to_thread(t->stack_current, &current->stack_current); } @@ -279,7 +262,7 @@ t->id = 0; t->can_yield = 1; - stack_top = &thread_stacks[CONFIG_STACK_SIZE] - sizeof(struct cpu_info); + stack_top = &thread_stacks[CONFIG_STACK_SIZE]; for (i = 1; i < TOTAL_NUM_THREADS; i++) { t = &all_threads[i]; t->stack_orig = (uintptr_t)stack_top; -- To view, visit https://review.coreboot.org/c/coreboot/+/57628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a Gerrit-Change-Number: 57628 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86,cpu/x86: Introduce new method for accessing cpu_info
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57627 ) Change subject: arch/x86,cpu/x86: Introduce new method for accessing cpu_info ...................................................................... arch/x86,cpu/x86: Introduce new method for accessing cpu_info There is currently a fundamental flaw in the current cpu_info() implementation. It assumes that current stack is CONFIG_STACK_SIZE aligned. This assumption breaks down when performing SMM relocation. The first step in performing SMM relocation is changing the SMBASE. This is accomplished by installing the smmstub at 0x00038000, which is the default SMM entry point. The stub is configured to set up a new stack with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point of smm_do_relocation located in RAMSTAGE RAM. This means that when smm_do_relocation is executed, it is running in SMM with a different sized stack. When cpu_info() gets called it will be using CONFIG_STACK_SIZE to calculate the location of the cpu_info struct. This results in reading random memory. Since cpu_info() has to run in multiple environments, we can't use a compile time constant to locate the cpu_info struct. This CL introduces a new way of locating cpu_info. It uses a per-cpu segment descriptor that points to a per-cpu segment that is allocated on the stack. By using a segment descriptor to point to the per-cpu data, we no longer need to calculate the location of the cpu_info struct. This has the following advantages: * Stacks no longer need to be CONFIG_STACK_SIZE aligned. * Accessing an unconfigured segment will result in an exception. This ensures no one can call cpu_info() from an unsupported environment. * Segment selectors are cleared when entering SMM and restored when leaving SMM. * There is a 1:1 mapping between cpu and cpu_info. When using COOP_MULTITASKING, a new cpu_info is currently allocated at the top of each thread's stack. This no longer needs to happen. This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so reviewers can feel more comfortable knowing most of the CL is a no-op. I would eventually like to remove most of the guards though. This CL does not touch the LEGACY_SMP_INIT code path. I don't have any way of testing it. The %gs segment was chosen over the %fs segment because it's what the linux kernel uses for per-cpu data in x86_64 mode. BUG=b:194391185, b:179699789 TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct %gs segment. Verify cpu_info looks sane. Verify booting to the OS works correctly with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Peers <epeers(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/arch/x86/c_start.S M src/arch/x86/include/arch/cpu.h M src/cpu/x86/Kconfig M src/cpu/x86/cpu_info.S.inc M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/gdt.h 8 files changed, 186 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Peers: Looks good to me, but someone else must approve diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index cb7d504..9e718fc 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -80,6 +80,20 @@ push_cpu_info +#if CONFIG(CPU_INFO_V2) + /* Allocate the per_cpu_segment_data on the stack */ + push_per_cpu_segment_data + + /* + * Update the BSP's per_cpu_segment_descriptor to point to the + * per_cpu_segment_data that was allocated on the stack. + */ + set_segment_descriptor_base $per_cpu_segment_descriptors, %esp + + mov per_cpu_segment_selector, %eax + mov %eax, %gs +#endif + /* * Now we are finished. Memory is up, data is copied and * bss is cleared. Now we call the main routine and @@ -127,6 +141,7 @@ #endif .globl gdt, gdt_end + .global per_cpu_segment_descriptors, per_cpu_segment_selector gdtaddr: .word gdt_end - gdt - 1 @@ -136,7 +151,7 @@ .long gdt /* we know the offset */ #endif - .data + .data /* This is the gdt for GCC part of coreboot. * It is different from the gdt in ASM part of coreboot @@ -206,8 +221,26 @@ .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0xaf, 0x00 #endif +#if CONFIG(CPU_INFO_V2) +per_cpu_segment_descriptors: + .rept CONFIG_MAX_CPUS + /* flat data segment */ + .word 0xffff, 0x0000 +#if ENV_X86_64 + .byte 0x00, 0x92, 0xcf, 0x00 +#else + .byte 0x00, 0x93, 0xcf, 0x00 +#endif + .endr +#endif /* CPU_INFO_V2 */ gdt_end: +#if CONFIG(CPU_INFO_V2) +/* Segment selector pointing to the first per_cpu_segment_descriptor. */ +per_cpu_segment_selector: + .long per_cpu_segment_descriptors - gdt +#endif /* CPU_INFO_V2 */ + .section ".text._start", "ax", @progbits #if ENV_X86_64 SetCodeSelector: diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index f736a14..8e96fae 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -236,11 +236,40 @@ #endif }; +/* + * This structure describes the data allocated in the %gs segment for each CPU. + * In order to read from this structure you will need to use assembly to + * reference the segment. + * + * e.g., Reading the cpu_info pointer: + * %%gs:0 + */ +struct per_cpu_segment_data { + /* + * Instead of keeping a `struct cpu_info`, we actually keep a pointer + * pointing to the cpu_info struct located in %ds. This prevents + * needing specific access functions to read the fields in the cpu_info. + */ + struct cpu_info *cpu_info; +}; + static inline struct cpu_info *cpu_info(void) { +/* We use a #if because we don't want to mess with the &s below. */ +#if CONFIG(CPU_INFO_V2) + struct cpu_info *ci = NULL; + + __asm__("mov %%gs:%c[offset], %[ci]" + : [ci] "=r" (ci) + : [offset] "i" (offsetof(struct per_cpu_segment_data, cpu_info)) + ); + + return ci; +#else char s; uintptr_t info = ALIGN_UP((uintptr_t)&s, CONFIG_STACK_SIZE) - sizeof(struct cpu_info); return (struct cpu_info *)info; +#endif /* CPU_INFO_V2 */ } struct cpuinfo_x86 { diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index a5c2a4d..99e33bb 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -193,3 +193,11 @@ the system BIOS and the last 2 are to be reserved for OS usage. However, modern OSes use PAT to control cacheability instead of using MTRRs. + +config CPU_INFO_V2 + bool + depends on PARALLEL_MP + help + Enables the new method of locating struct cpu_info. This new method + uses the %gs segment to locate the cpu_info pointer. The old method + relied on the stack being CONFIG_STACK_SIZE aligned. diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc index 62b47ca..dffd1bc 100644 --- a/src/cpu/x86/cpu_info.S.inc +++ b/src/cpu/x86/cpu_info.S.inc @@ -8,3 +8,50 @@ push \index /* index */ push $0 /* *cpu */ .endm + +/* Push struct per_cpu_segment_data */ +.macro push_per_cpu_segment_data cpu_info_pointer=%esp + push \cpu_info_pointer /* *cpu_info */ +.endm + +/* + * Sets the base address in the segment descriptor array. + * + * A segment descriptor has the following structure: + * struct { + * uint16_t segment_limit_0_15; + * uint16_t base_address_0_15; + * uint8_t base_address_16_23; + * uint8_t attrs[2]; + * uint8_t base_address_24_31; + * }; + * + * @desc_array: Address of the descriptor table + * @base: Address to set in the descriptor + * @desc_index: Index of the descriptor in the table. Defaults to 0. Must be a + * register if specified. + * + * Clobbers %eax. + */ +.macro set_segment_descriptor_base desc_array:req, base:req, desc_index + mov \base, %eax + + push %ebx /* preserve ebx */ + mov \desc_array, %ebx + +.ifb \desc_index + movw %ax, 2(%ebx) + shr $16, %eax + movb %al, 4(%ebx) + shr $8, %eax + movb %al, 7(%ebx) +.else + movw %ax, 2(%ebx, \desc_index, 8) + shr $16, %eax + movb %al, 4(%ebx, \desc_index, 8) + shr $8, %eax + movb %al, 7(%ebx, \desc_index, 8) +.endif + + pop %ebx +.endm diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 93c143e..123b2b5 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -89,6 +89,8 @@ uint32_t gdt; uint16_t unused; uint32_t idt_ptr; + uint32_t per_cpu_segment_descriptors; + uint32_t per_cpu_segment_selector; uint32_t stack_top; uint32_t stack_size; uint32_t microcode_lock; /* 0xffffffff means parallel loading. */ @@ -215,10 +217,20 @@ sp->gdt = (uintptr_t)&gdt; sp->gdtlimit = (uintptr_t)&gdt_end - (uintptr_t)&gdt - 1; sp->idt_ptr = (uintptr_t)&idtarg; + if (CONFIG(CPU_INFO_V2)) { + sp->per_cpu_segment_descriptors = (uintptr_t)&per_cpu_segment_descriptors; + sp->per_cpu_segment_selector = per_cpu_segment_selector; + } sp->stack_size = CONFIG_STACK_SIZE; sp->stack_top = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE); - /* Adjust the stack top to take into account cpu_info. */ - sp->stack_top -= sizeof(struct cpu_info); + /* + * In the CPU_INFO_V2 case, we don't need to pre-allocate the space on the stack. + * Instead we push them onto the top of the stack in the sipi vector. + */ + if (!CONFIG(CPU_INFO_V2)) { + /* Adjust the stack top to take into account cpu_info. */ + sp->stack_top -= sizeof(struct cpu_info); + } } #define NUM_FIXED_MTRRS 11 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 496fd34..491f1de 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/x86/cpu_info.S.inc> #include <cpu/x86/cr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> @@ -19,6 +20,10 @@ .word 0 /* unused */ idt_ptr: .long 0 +per_cpu_segment_descriptors: +.long 0 +per_cpu_segment_selector: +.long 0 stack_top: .long 0 stack_size: @@ -98,6 +103,23 @@ movl stack_top, %edx subl %eax, %edx mov %edx, %esp + +#if CONFIG(CPU_INFO_V2) + push_cpu_info index=%ecx + push_per_cpu_segment_data + + /* + * Update the AP's per_cpu_segment_descriptor to point to the + * per_cpu_segment_data that was allocated on the stack. + */ + set_segment_descriptor_base per_cpu_segment_descriptors, %esp, %ecx + + mov %ecx, %eax + shl $3, %eax /* The index is << 3 in the segment selector */ + add per_cpu_segment_selector, %eax + mov %eax, %gs +#endif + andl $0xfffffff0, %esp /* ensure stack alignment */ /* Save CPU number. */ diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index aa48ab6..e409983 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -9,6 +9,7 @@ * found in smm.h. */ +#include <cpu/x86/cpu_info.S.inc> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic_def.h> @@ -82,8 +83,21 @@ /* gdt selector 0x20 tss segment */ .word 0xffff, 0x0000 .byte 0x00, 0x8b, 0x80, 0x00 + +#if CONFIG(CPU_INFO_V2) +per_cpu_segment_descriptors: + .rept CONFIG_MAX_CPUS + /* selgdt 0x28, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + .endr +#endif /* CPU_INFO_V2 */ smm_relocate_gdt_end: +#if CONFIG(CPU_INFO_V2) +.set per_cpu_segment_selector, per_cpu_segment_descriptors - smm_relocate_gdt +#endif /* CPU_INFO_V2 */ + .align 4 .code32 .global smm_trampoline32 @@ -153,6 +167,22 @@ movl $0, 4(%ebx) #endif +#if CONFIG(CPU_INFO_V2) + push_cpu_info index=%ecx + push_per_cpu_segment_data + + /* + * Update the AP's per_cpu_segment_descriptor to point to the + * per_cpu_segment_data that was allocated on the stack. + */ + set_segment_descriptor_base $per_cpu_segment_descriptors, %esp, %ecx + + mov %ecx, %eax + shl $3, %eax /* The index is << 3 in the segment selector */ + add $per_cpu_segment_selector, %eax + mov %eax, %gs +#endif + /* Create stack frame by pushing a NULL stack base pointer */ pushl $0x0 mov %esp, %ebp diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h index bc4eaad..27a863e 100644 --- a/src/include/cpu/x86/gdt.h +++ b/src/include/cpu/x86/gdt.h @@ -5,6 +5,8 @@ /* These symbols are defined in c_start.S. */ extern char gdt[]; +extern char per_cpu_segment_descriptors[]; +extern uint32_t per_cpu_segment_selector; extern char gdt_end[]; extern char idtarg[]; -- To view, visit https://review.coreboot.org/c/coreboot/+/57627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98 Gerrit-Change-Number: 57627 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common: Add support to read and set SPI speeds from verstage
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58115 ) Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/psp/psp_efs.c: https://review.coreboot.org/c/coreboot/+/58115/comment/361a31a6_99effe81 PS1, Line 14: efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs)); > This hard-coded EFS address works in x86. […] Oh that's not confusing. This file is under /psp and called psp_efs. I thought it was only called from PSP verstage. Can you delete the EFS_ADDRESS #define since we shouldn't need it anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/58115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I281531e506b56173471b918c746f58d1ad97162c Gerrit-Change-Number: 58115 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Oct 2021 22:38:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Refactor ESPI Setup
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58114 ) Change subject: soc/amd/cezanne: Refactor ESPI Setup ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/early_fch.c: https://review.coreboot.org/c/coreboot/+/58114/comment/d922acdd_50d858d9 PS1, Line 47: lpc_early_init > Post Codes need to be routed before bootblock hit this point. […] Who is writing port 80s before this? I wasn't able to find any callers -- To view, visit https://review.coreboot.org/c/coreboot/+/58114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Gerrit-Change-Number: 58114 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Oct 2021 22:34:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: adlrvp_m: Enable eNEM
by Bora Guvendik (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Selma Bensaid. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57323 ) Change subject: adlrvp_m: Enable eNEM ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/57323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b Gerrit-Change-Number: 57323 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 22:32:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
by Michael Niewöhner (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 ) Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: ey buildbot... do you need to spam THAT much!? -- To view, visit https://review.coreboot.org/c/coreboot/+/57886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06 Gerrit-Change-Number: 57886 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt Delco <delco(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Oct 2021 22:21:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
by build bot (Jenkins) (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Patrick Rudolph, Lance Zhao, Jason Glenesk, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58118 ) Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing ...................................................................... Patch Set 2: (94 comments) File src/cpu/intel/common/common_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/a742914d_5cdca1f9 PS2, Line 105: [CPPC_HIGHEST_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/c4b7f182_173f23fe PS2, Line 105: [CPPC_HIGHEST_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/a04258aa_5500ceed PS2, Line 106: [CPPC_NOMINAL_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_PLATFORM_INFO, 8, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/2f9a77ad_35499712 PS2, Line 106: [CPPC_NOMINAL_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_PLATFORM_INFO, 8, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/25dbe420_1de8af95 PS2, Line 107: [CPPC_LOWEST_NONL_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/d8268dcc_50aa4e72 PS2, Line 107: [CPPC_LOWEST_NONL_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/90a1ef6b_76512f8d PS2, Line 107: [CPPC_LOWEST_NONL_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/8ad56b32_4b994d8e PS2, Line 108: [CPPC_LOWEST_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/a9769e34_8522707b PS2, Line 108: [CPPC_LOWEST_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/b525373e_3b141ba6 PS2, Line 108: [CPPC_LOWEST_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/27b63d3b_299f60d1 PS2, Line 109: [CPPC_GUARANTEED_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/ba66d600_93387e88 PS2, Line 109: [CPPC_GUARANTEED_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/4596b5ee_d06fbb88 PS2, Line 110: [CPPC_DESIRED_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 16, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/b6d977d0_917ab765 PS2, Line 110: [CPPC_DESIRED_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 16, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/575ab08b_701832fb PS2, Line 111: [CPPC_MIN_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 0, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/a9551715_00217b56 PS2, Line 111: [CPPC_MIN_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 0, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/5cbcd9e0_26761eb1 PS2, Line 112: [CPPC_MAX_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 8, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/0ff18518_58db9370 PS2, Line 112: [CPPC_MAX_PERF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 8, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/e17049bd_000cc85a PS2, Line 113: [CPPC_PERF_REDUCE_TOLERANCE] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/f8772ce5_030936c7 PS2, Line 113: [CPPC_PERF_REDUCE_TOLERANCE] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/250052ea_9c63ea1f PS2, Line 114: [CPPC_TIME_WINDOW] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/4a9d3190_20528934 PS2, Line 114: [CPPC_TIME_WINDOW] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/467a48b1_6e77a722 PS2, Line 115: [CPPC_COUNTER_WRAP] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/07a80cab_760c6997 PS2, Line 115: [CPPC_COUNTER_WRAP] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/e25b7022_85b0f37a PS2, Line 116: [CPPC_REF_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(IA32_MPERF, 0, 64) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/d789c7ad_f8f362ea PS2, Line 116: [CPPC_REF_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(IA32_MPERF, 0, 64) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/c3eb236d_7b64dfe8 PS2, Line 117: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(IA32_APERF, 0, 64) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/0275e391_fb1b20e1 PS2, Line 117: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(IA32_APERF, 0, 64) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/b43e94c6_870f0e70 PS2, Line 118: [CPPC_PERF_LIMITED] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_STATUS, 2, 1) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/8114ad6c_90f9be02 PS2, Line 118: [CPPC_PERF_LIMITED] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_STATUS, 2, 1) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/ccd1c4bb_00b67ce5 PS2, Line 119: [CPPC_ENABLE] = CPPC_REG( ACPI_REG_MSR(IA32_PM_ENABLE, 0, 1) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/4afb345a_3b1d5b26 PS2, Line 119: [CPPC_ENABLE] = CPPC_REG( ACPI_REG_MSR(IA32_PM_ENABLE, 0, 1) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/d3c06abc_32bf4cef PS2, Line 123: [CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/bb938703_887b25c9 PS2, Line 123: [CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/823b4626_9465fbef PS2, Line 124: [CPPC_PERF_PREF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 24, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/49183c84_ec242de6 PS2, Line 124: [CPPC_PERF_PREF] = CPPC_REG( ACPI_REG_MSR(IA32_HWP_REQUEST, 24, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/dfae96ca_91d1fb40 PS2, Line 125: [CPPC_REF_PERF] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/06d9c297_bd607991 PS2, Line 125: [CPPC_REF_PERF] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/806d1aac_902349b9 PS2, Line 128: [CPPC_LOWEST_FREQ] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/5be18b9c_957db03f PS2, Line 128: [CPPC_LOWEST_FREQ] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/8c3c79bf_9bd19b6f PS2, Line 129: [CPPC_NOMINAL_FREQ] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/6e22afc9_ee2c6d7b PS2, Line 129: [CPPC_NOMINAL_FREQ] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' File src/soc/amd/cezanne/cppc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/27211d05_f7bb2157 PS2, Line 15: [CPPC_HIGHEST_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/c39a9554_ac2635ab PS2, Line 15: [CPPC_HIGHEST_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/3fbe2ffb_5a4cff02 PS2, Line 15: [CPPC_HIGHEST_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/4cd37c25_9d742c98 PS2, Line 16: [CPPC_NOMINAL_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/758fb409_fc2babdb PS2, Line 16: [CPPC_NOMINAL_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/924d72e6_26dc7826 PS2, Line 16: [CPPC_NOMINAL_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/63397322_1688d534 PS2, Line 17: [CPPC_LOWEST_NONL_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/cd60c10a_1913c974 PS2, Line 17: [CPPC_LOWEST_NONL_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/a7d79808_d838fdbe PS2, Line 17: [CPPC_LOWEST_NONL_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/5f6c63e4_9022bda9 PS2, Line 18: [CPPC_LOWEST_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/f4e996e7_c7efb26b PS2, Line 18: [CPPC_LOWEST_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/79e1b2a5_3652b5d7 PS2, Line 18: [CPPC_LOWEST_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/d034f38b_d1d302d4 PS2, Line 19: [CPPC_GUARANTEED_PERF] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/c419fb1c_da3d478a PS2, Line 19: [CPPC_GUARANTEED_PERF] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/272429da_5abbb4b3 PS2, Line 20: [CPPC_DESIRED_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/1b6cc06c_71316598 PS2, Line 20: [CPPC_DESIRED_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/963ff49d_ec2022cd PS2, Line 20: [CPPC_DESIRED_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/413a07d0_a08f1aab PS2, Line 21: [CPPC_MIN_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/2539daba_adea4839 PS2, Line 21: [CPPC_MIN_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/78960ea6_fcb41ab5 PS2, Line 21: [CPPC_MIN_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/cde5189e_a308e9cc PS2, Line 22: [CPPC_MAX_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/a7f1213d_90974f65 PS2, Line 22: [CPPC_MAX_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/2952b104_b48c2e6d PS2, Line 22: [CPPC_MAX_PERF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/0d5228d3_43e7e632 PS2, Line 23: [CPPC_PERF_REDUCE_TOLERANCE] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/08f56622_536a22f8 PS2, Line 23: [CPPC_PERF_REDUCE_TOLERANCE] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/748fc11c_f91d202c PS2, Line 24: [CPPC_TIME_WINDOW] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/79766c77_9a2eddfc PS2, Line 24: [CPPC_TIME_WINDOW] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/e5616a7e_e88b5375 PS2, Line 25: [CPPC_COUNTER_WRAP] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/47250889_60632b86 PS2, Line 25: [CPPC_COUNTER_WRAP] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/1ef51eac_5ec9718c PS2, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/d39f2b1f_f7fa5f5b PS2, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/6c7dbf1f_5f963c15 PS2, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/91740026_2f6ff0cf PS2, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/446c804e_59c0c4c8 PS2, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/5efea3f6_7c34b040 PS2, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/bcfb081b_b47bf18d PS2, Line 28: [CPPC_PERF_LIMITED] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_STATUS, 1, 1) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/0528ea30_cf5404fa PS2, Line 28: [CPPC_PERF_LIMITED] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_STATUS, 1, 1) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/6c2b8e71_c1ef7740 PS2, Line 29: [CPPC_ENABLE] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_ENABLE, 0, 1) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/af594b70_4315edfa PS2, Line 29: [CPPC_ENABLE] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_ENABLE, 0, 1) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/74b7df83_9de79a66 PS2, Line 32: [CPPC_AUTO_SELECT] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/05a5e002_f8191386 PS2, Line 32: [CPPC_AUTO_SELECT] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/35dfa927_641bb0d8 PS2, Line 33: [CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/ea8b823f_f89bd099 PS2, Line 33: [CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/2a9e2fd7_2bfb80f9 PS2, Line 34: [CPPC_PERF_PREF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8) ), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/128a1d16_ef09ad0b PS2, Line 34: [CPPC_PERF_PREF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8) ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/b9c0166b_ea2eb101 PS2, Line 34: [CPPC_PERF_PREF] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8) ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/2579f768_b9a9e3cb PS2, Line 35: [CPPC_REF_PERF] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/33babcc3_921754f6 PS2, Line 35: [CPPC_REF_PERF] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/3d1c744a_42fff337 PS2, Line 38: [CPPC_LOWEST_FREQ] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/2862b7cf_9bb329f1 PS2, Line 38: [CPPC_LOWEST_FREQ] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/b5cdcd5c_e7f76355 PS2, Line 39: [CPPC_NOMINAL_FREQ] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129831): https://review.coreboot.org/c/coreboot/+/58118/comment/8559b0fa_1148f200 PS2, Line 39: [CPPC_NOMINAL_FREQ] = CPPC_REG( ACPI_REG_UNSUPPORTED ), space prohibited before that close parenthesis ')' -- To view, visit https://review.coreboot.org/c/coreboot/+/58118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26c5e80c2a16a50ed73245c7c32d61b17e45c22a Gerrit-Change-Number: 58118 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Oct 2021 22:19:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2021