Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58114 )
Change subject: soc/amd/cezanne: Refactor ESPI Setup
......................................................................
soc/amd/cezanne: Refactor ESPI Setup
ESPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also ESPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating ESPI at bootblock entry if verified boot starts after
bootblock.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
---
M src/soc/amd/cezanne/bootblock.c
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/cezanne/include/soc/southbridge.h
3 files changed, 7 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/58114/1
diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c
index fc1c5e7c..def0a78 100644
--- a/src/soc/amd/cezanne/bootblock.c
+++ b/src/soc/amd/cezanne/bootblock.c
@@ -92,12 +92,11 @@
set_caching();
write_resume_eip();
enable_pci_mmconf();
- /*
- * If NO_EARLY_BOOTBLOCK_POSTCODES is selected, we need to initialize port80h
- * routing as early as possible
- */
- if (CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
- configure_port80_routing_early();
+
+ /* If ESPI is setup in PSP Verstage, continue with that. Else setup ESPI to perform
+ port80h routing as early as possible. */
+ if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
+ configure_espi();
/*
* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index bddcbee..834ca70 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -33,7 +33,7 @@
}
/* Initialize port80h routing early if needed */
-void configure_port80_routing_early(void)
+void configure_espi(void)
{
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
mb_set_up_early_espi();
@@ -78,7 +78,4 @@
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
-
- if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
- espi_setup();
}
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 31387b6..3dfad54 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -107,7 +107,7 @@
#define I2C_PAD_CTRL_SPARE0 BIT(17)
#define I2C_PAD_CTRL_SPARE1 BIT(18)
-void configure_port80_routing_early(void);
+void configure_espi(void);
void fch_pre_init(void);
void fch_early_init(void);
void fch_init(void *chip_info);
--
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Gerrit-Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Gerrit-Change-Number: 58114
Gerrit-PatchSet: 1
Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>
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Attention is currently required from: Bora Guvendik, Anil Kumar K, Tim Wawrzynczak, Selma Bensaid, Raju Rajakumar.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57863 )
Change subject: mb/intel/adlrvp_m: Enable touchpad
......................................................................
Patch Set 4: Verified-1
(2 comments)
File src/mainboard/intel/adlrvp/gpio_m.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129817):
https://review.coreboot.org/c/coreboot/+/57863/comment/d7dbdc95_4d2f6267
PS4, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP),
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129817):
https://review.coreboot.org/c/coreboot/+/57863/comment/fcb6dff8_48ba1eef
PS4, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP),
please, no spaces at the start of a line
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57863 )
Change subject: mb/intel/adlrvp_m: Enable touchpad
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/intel/adlrvp/gpio_m.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129816):
https://review.coreboot.org/c/coreboot/+/57863/comment/9c4f54de_26a75e1e
PS3, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP),
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129816):
https://review.coreboot.org/c/coreboot/+/57863/comment/03ddc485_c7402c2f
PS3, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP),
please, no spaces at the start of a line
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Bernardo Perez Priego has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58113 )
Change subject: mb/intel/adlrvp_m: Enable retimer force power gpio
......................................................................
mb/intel/adlrvp_m: Enable retimer force power gpio
Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain
to toggle during a switch from DP Alt to TBT Alt modes.
Contrary to DS specifying it may be left unconfigured, hence floating, there are instances
seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp).
Hence configure it to LOW.
Branch=none
Bug=none
Test=Boot to OS, connect TBT dock which enumerates in DP Alt,
Login, TBT dock enumerates in TBT Alt
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c
---
M src/mainboard/intel/adlrvp/gpio_m.c
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/58113/2
--
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57863
to look at the new patch set (#3).
Change subject: mb/intel/adlrvp_m: Enable touchpad
......................................................................
mb/intel/adlrvp_m: Enable touchpad
This changes will include ELAN touchpad to ACPI tables and configure GPIO's.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e
---
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/adlrvp/gpio_m.c
2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/57863/3
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Gerrit-Change-Number: 57863
Gerrit-PatchSet: 3
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58113 )
Change subject: mb/intel/adlrvp_m: Enable retimer force power gpio
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/intel/adlrvp/gpio_m.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129815):
https://review.coreboot.org/c/coreboot/+/58113/comment/de96136b_2c8d2e49
PS1, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP)
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129815):
https://review.coreboot.org/c/coreboot/+/58113/comment/06c59065_9edd2e8a
PS1, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP)
please, no spaces at the start of a line
--
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