coreboot-gerrit October 2021

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Change in coreboot[master]: soc/amd/common: Add support to read and set SPI speeds from verstage
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58115 ) Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/psp/psp_efs.c: https://review.coreboot.org/c/coreboot/+/58115/comment/d15719c4_27916827 PS1, Line 14: efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs)); What is the reasoning for changing this? -- To view, visit https://review.coreboot.org/c/coreboot/+/58115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I281531e506b56173471b918c746f58d1ad97162c Gerrit-Change-Number: 58115 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Oct 2021 21:16:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Refactor ESPI Setup
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58114 ) Change subject: soc/amd/cezanne: Refactor ESPI Setup ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/early_fch.c: https://review.coreboot.org/c/coreboot/+/58114/comment/0ed294a3_999bd6fc PS1, Line 47: lpc_early_init One thing I've always wondered is why can't we call configure_espi here? -- To view, visit https://review.coreboot.org/c/coreboot/+/58114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Gerrit-Change-Number: 58114 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Oct 2021 21:14:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/tigerlake: Make IO decode / enable register configurable
by Nico Huber (Code Review) 05 Oct '21

05 Oct '21

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57140 ) Change subject: soc/tigerlake: Make IO decode / enable register configurable ...................................................................... Patch Set 19: (1 comment) Patchset: PS19: > Do you mean […] Yep. The only difference for newer platforms is that there are these DMI registers that need the values mirrored. I don't see the need for the complex soc/intel/common/ code, neither for anything platform specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/57140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3 Gerrit-Change-Number: 57140 Gerrit-PatchSet: 19 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 05 Oct 2021 20:54:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Override SPI Fast speeds
by Karthik Ramasubramanian (Code Review) 05 Oct '21

05 Oct '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58117 ) Change subject: mb/google/guybrush: Override SPI Fast speeds ...................................................................... mb/google/guybrush: Override SPI Fast speeds Add support to override SPI fast speeds based on board version from both bootblock and verstage. Overrides apply for Guybrush only and SPI speed is overridden from 66 MHz to 100 MHz starting board version 4. This will help to improve the boot time on board version by ~60 ms and still allow the old boards to boot with 66 MHz. BUG=b:199779306 TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/bootblock.c M src/mainboard/google/guybrush/verstage.c 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/58117/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index c259d25..e5f1382 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -111,6 +111,22 @@ config ALT_SPI_SPEED default 0 # 66MHz +config OVERRIDE_EFS_SPI_SPEED + int + default 3 if EM100 + default 4 # 100MHz + help + Override EFS SPI Speed Configuration to be applied based on certain + board version. + +config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD + hex + default 0x4 if BOARD_GOOGLE_GUYBRUSH + default 0xffffffff + help + Minimum board version starting which the Override EFS SPI Speed + configuration has to be applied. + endif # !EM100 config VARIANT_DIR diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index cd27632..f4fff1f 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -2,8 +2,10 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> +#include <amdblocks/spi.h> #include <bootblock_common.h> #include <baseboard/variants.h> +#include <boardid.h> #include <console/console.h> #include <delay.h> #include <device/pci_ops.h> @@ -92,3 +94,12 @@ if (variant_has_fpmcu()) variant_fpmcu_reset(); } + + +void mainboard_spi_fast_speed_override(uint8_t *fast_speed) +{ + uint32_t board_ver = board_id(); + + if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) + *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; +} diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index aaaaf03..afc2a10 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -2,8 +2,10 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/gpio.h> +#include <amdblocks/spi.h> #include <arch/io.h> #include <baseboard/variants.h> +#include <boardid.h> #include <security/vboot/vboot_common.h> static void setup_gpio(void) @@ -38,3 +40,12 @@ pm_io_write32(0x74, dword); } } + +void mainboard_spi_fast_speed_override(uint8_t *fast_speed) +{ + uint32_t board_ver = board_id(); + + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && + board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) + *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2 Gerrit-Change-Number: 58117 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/spi: Support fast speed override
by Karthik Ramasubramanian (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58116 ) Change subject: soc/amd/common/block/spi: Support fast speed override ...................................................................... soc/amd/common/block/spi: Support fast speed override Add support to override SPI ROM fast speed based on board version. This will allow boards to start at lower speeds during bringup and then switch to higher speeds after assessing the signal integrity. Also implement a default no-op override. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304 --- M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/fch_spi.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/58116/1 diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index eaea0f7..35a3782 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -117,4 +117,5 @@ void spi_write32(uint8_t reg, uint32_t val); void fch_spi_config_modes(void); +void mainboard_spi_fast_speed_override(uint8_t *fast_speed); #endif /* AMD_BLOCK_SPI_H */ diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 51787fae..6757f36 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -50,6 +50,11 @@ printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]); } +void __weak mainboard_spi_fast_speed_override(uint8_t *unused) +{ + /* No overriding SPI speeds. */ +} + static uint8_t lower_speed(uint8_t speed1, uint8_t speed2) { uint8_t speeds[] = {SPI_SPEED_800K, SPI_SPEED_16M, SPI_SPEED_22M, @@ -102,6 +107,7 @@ read_mode = CONFIG_EFS_SPI_READ_MODE; fast_speed = CONFIG_EFS_SPI_SPEED; } + mainboard_spi_fast_speed_override(&fast_speed); if (fast_speed != CONFIG_EFS_SPI_SPEED) { normal_speed = lower_speed(normal_speed, fast_speed); -- To view, visit https://review.coreboot.org/c/coreboot/+/58116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304 Gerrit-Change-Number: 58116 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Add support to read and set SPI speeds from verstage
by Karthik Ramasubramanian (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58115 ) Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage ...................................................................... soc/amd/common: Add support to read and set SPI speeds from verstage Currently all SPI speed configurations are done through EFS at build time. There is a need to apply SPI speed overrides at run-time - eg. based on board version after assessing the signal integrity. This override configuration can be carried out by PSP verstage and bootblock. Export the APIs to set and read SPI speeds from both PSP verstage and bootblock. BUG=None TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I281531e506b56173471b918c746f58d1ad97162c --- M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/psp/Makefile.inc M src/soc/amd/common/block/psp/psp_efs.c M src/soc/amd/common/block/spi/fch_spi.c M src/soc/amd/common/psp_verstage/fch.c 5 files changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/58115/1 diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index c4ad44f..eaea0f7 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -116,4 +116,5 @@ void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); +void fch_spi_config_modes(void); #endif /* AMD_BLOCK_SPI_H */ diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index db9ebda..2b407a2 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -23,5 +23,6 @@ smm-y += psp_smm_gen2.c bootblock-y += psp_efs.c +verstage-y += psp_efs.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c index b0397f6..5814f48 100644 --- a/src/soc/amd/common/block/psp/psp_efs.c +++ b/src/soc/amd/common/block/psp/psp_efs.c @@ -2,13 +2,18 @@ #include <amdblocks/psp_efs.h> #include <arch/mmio.h> +#include <boot_device.h> +#include <commonlib/region.h> #include <types.h> -struct _embedded_firmware *efs = (struct _embedded_firmware *)EFS_ADDRESS; +static struct _embedded_firmware *efs; bool efs_is_valid(void) { - if (efs->signature != EMBEDDED_FW_SIGNATURE) + if (!efs) + efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs)); + + if (!efs || efs->signature != EMBEDDED_FW_SIGNATURE) return false; return true; diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 38be7be..51787fae 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -91,7 +91,7 @@ spi_write32(SPI_CNTRL0, val | SPI_READ_MODE(mode)); } -static void fch_spi_config_modes(void) +void fch_spi_config_modes(void) { uint8_t read_mode, fast_speed; uint8_t normal_speed = CONFIG_NORMAL_READ_SPI_SPEED; diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index c74e88fd..f578bcb 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -161,4 +161,6 @@ printk(BIOS_DEBUG, "Setting up i2c\n"); i2c_soc_early_init(); printk(BIOS_DEBUG, "i2c setup\n"); + fch_spi_config_modes(); + show_spi_speeds_and_modes(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I281531e506b56173471b918c746f58d1ad97162c Gerrit-Change-Number: 58115 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Refactor ESPI Setup
by Karthik Ramasubramanian (Code Review) 05 Oct '21

05 Oct '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58114 ) Change subject: soc/amd/cezanne: Refactor ESPI Setup ...................................................................... soc/amd/cezanne: Refactor ESPI Setup ESPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also ESPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating ESPI at bootblock entry if verified boot starts after bootblock. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 --- M src/soc/amd/cezanne/bootblock.c M src/soc/amd/cezanne/early_fch.c M src/soc/amd/cezanne/include/soc/southbridge.h 3 files changed, 7 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/58114/1 diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c index fc1c5e7c..def0a78 100644 --- a/src/soc/amd/cezanne/bootblock.c +++ b/src/soc/amd/cezanne/bootblock.c @@ -92,12 +92,11 @@ set_caching(); write_resume_eip(); enable_pci_mmconf(); - /* - * If NO_EARLY_BOOTBLOCK_POSTCODES is selected, we need to initialize port80h - * routing as early as possible - */ - if (CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)) - configure_port80_routing_early(); + + /* If ESPI is setup in PSP Verstage, continue with that. Else setup ESPI to perform + port80h routing as early as possible. */ + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + configure_espi(); /* * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index bddcbee..834ca70 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -33,7 +33,7 @@ } /* Initialize port80h routing early if needed */ -void configure_port80_routing_early(void) +void configure_espi(void) { if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { mb_set_up_early_espi(); @@ -78,7 +78,4 @@ if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); - - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)) - espi_setup(); } diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 31387b6..3dfad54 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -107,7 +107,7 @@ #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) -void configure_port80_routing_early(void); +void configure_espi(void); void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/58114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Gerrit-Change-Number: 58114 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: don't force-use `python2`
by Felix Singer (Code Review) 05 Oct '21

05 Oct '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58088 ) Change subject: drivers/intel/fsp2_0: don't force-use `python2` ...................................................................... drivers/intel/fsp2_0: don't force-use `python2` Some distributions (e.g. NixOS, Debian) are actively working on getting rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and Python 3 as of upstream commit 0bc2b07, use whatever version is present by utilizing `python`. Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/drivers/intel/fsp2_0/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 01b4c9e..92ebf24 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -78,7 +78,7 @@ ifeq ($(CONFIG_FSP_FULL_FD),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG) - python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" + python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true -- To view, visit https://review.coreboot.org/c/coreboot/+/58088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d Gerrit-Change-Number: 58088 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable touchpad
by build bot (Jenkins) (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Tim Wawrzynczak, Selma Bensaid, Raju Rajakumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57863 ) Change subject: mb/intel/adlrvp_m: Enable touchpad ...................................................................... Patch Set 4: Verified-1 (2 comments) File src/mainboard/intel/adlrvp/gpio_m.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129817): https://review.coreboot.org/c/coreboot/+/57863/comment/d7dbdc95_4d2f6267 PS4, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129817): https://review.coreboot.org/c/coreboot/+/57863/comment/fcb6dff8_48ba1eef PS4, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP), please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/57863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e Gerrit-Change-Number: 57863 Gerrit-PatchSet: 4 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Raju Rajakumar <raju.rajakumar(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Raju Rajakumar <raju.rajakumar(a)intel.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 19:27:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable touchpad
by build bot (Jenkins) (Code Review) 05 Oct '21

05 Oct '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57863 ) Change subject: mb/intel/adlrvp_m: Enable touchpad ...................................................................... Patch Set 3: (2 comments) File src/mainboard/intel/adlrvp/gpio_m.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129816): https://review.coreboot.org/c/coreboot/+/57863/comment/9c4f54de_26a75e1e PS3, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129816): https://review.coreboot.org/c/coreboot/+/57863/comment/03ddc485_c7402c2f PS3, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP), please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/57863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e Gerrit-Change-Number: 57863 Gerrit-PatchSet: 3 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Oct 2021 19:18:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2021