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Change subject: mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support
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Patch Set 1: Code-Review+1
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Change subject: mb/google/trogdor: Add new vaviant quackingstick
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58033/comment/9da42302_daf16ee0
PS1, Line 7: vaviant
> Done
Apparently it was not. What happened?
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Change subject: drivers/intel/dptf: Add support for PCH methods
......................................................................
drivers/intel/dptf: Add support for PCH methods
Add various methods support for pch device under dptf driver.
This provides support of different control knobs for FIVR.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/dptf/dptf.h
M src/soc/intel/alderlake/dptf.c
3 files changed, 164 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/57925/6
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Change subject: drivers/intel/dptf: Add support for PCH methods
......................................................................
Patch Set 5:
(2 comments)
File src/drivers/intel/dptf/dptf.c:
https://review.coreboot.org/c/coreboot/+/57925/comment/c1d07e12_0b57b376
PS4, Line 356: write_pkgc_method();
> But this will write out 5 copies of the PKGC Method won't it? Don't you see something in `dmesg` abo […]
Yes, you are correct. We do not need to do this inside for loop. Uploaded SSDT output on bug for your reference.
File src/drivers/intel/dptf/dptf.c:
https://review.coreboot.org/c/coreboot/+/57925/comment/a7568d5d_f5564823
PS5, Line 230: acpigen_write_package(1);
: acpigen_write_zero();
> Sorry I mean this seems like a separate change. […]
As per fsp code reference, we need this change for ESIF shell support.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/tcss: Optimize USB-C DP flow and code structure
......................................................................
soc/intel/common/tcss: Optimize USB-C DP flow and code structure
HPD event may not be ready when configuring TCSS mux for DP,
check if any DP device is connected and wait for HPD ready before
TCSS configuration. Remove unnecessary dependency on mainboard
functions, use generic interface which provides USB-C mux
operations.
BUG=b:192947843
TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name for
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`Port C%zd is configured to DP mode!` in coreboot log. Display
should show screen in developer mode or recovery mode.
Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com>
Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50
---
M src/soc/intel/common/block/include/intelblocks/tcss.h
M src/soc/intel/common/block/tcss/tcss.c
2 files changed, 44 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/57139/24
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Change subject: elog: Add a log for Chrome OS diagnostics boot in coreboot/bootmode
......................................................................
Patch Set 6:
(1 comment)
This change is ready for review.
Patchset:
PS6:
With the CL https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_refere… merged and the uprev, this CL satisfies its prerequisite
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Change subject: Update vboot submodule to upstream main
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Uprev for preparing adding an elog entry for diagnostic boot
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