coreboot-gerrit October 2021

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Change in coreboot[master]: Rename ECAM-specific MMCONF Kconfigs
by Shelley Chen (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Stefan Reinauer, Andrey Petrov, Patrick Rudolph, Lance Zhao, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Damien Zammit, Lee Leahy, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin, Morgan Jang, Michal Motyl, Alexander Couzens, Felix Held. Hello build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Stefan Reinauer, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Michal Motyl, Morgan Jang, Alexander Couzens, Felix Held, Furquan Shaikh, Angel Pons, Lance Zhao, Jason Glenesk, Damien Zammit, Martin Roth, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57333 to look at the new patch set (#6). Change subject: Rename ECAM-specific MMCONF Kconfigs ...................................................................... Rename ECAM-specific MMCONF Kconfigs Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space, which applies mainly to x86 platforms. This can be confusing as other platforms, such as ARM, have a different way of mapping the PCI config space to memory. Renaming the following configs to make it clearer the function of these configs: - NO_MMCONF_SUPPORT --> PCI_NO_MMIO_OPS: If this config is selected, the MMIO access for PCI config space is disabled. - MMCONF_SUPPORT --> PCI_ECAM: If this config is selected, then the platform supports the enhanced configuration access mechanism (ECAM). In this case, all PCI devices' config spaces are mapped to system memory. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/acpi/dsdt_top.asl M src/arch/x86/include/arch/pci_io_cfg.h M src/device/Kconfig M src/drivers/intel/fsp1_1/romstage.c M src/include/device/pci_mmio_cfg.h M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/bootblock.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/sandybridge/bootblock.c M src/soc/cavium/cn81xx/Kconfig M src/soc/example/min86/Kconfig M src/soc/intel/broadwell/bootblock.c M src/soc/intel/quark/Kconfig 17 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57333/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/57333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Gerrit-Change-Number: 57333 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55294 ) Change subject: soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Are we sure this wasn't a documentation error? Seems strange they would change the hardware like that. -- To view, visit https://review.coreboot.org/c/coreboot/+/55294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d Gerrit-Change-Number: 55294 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Oct 2021 17:11:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: simplify LPC_MISC_CONTROL_BITS update
by Raul Rangel (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Martin Roth, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58069 ) Change subject: mb/google/guybrush: simplify LPC_MISC_CONTROL_BITS update ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a Gerrit-Change-Number: 58069 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Oct 2021 17:07:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support
by Karthik Ramasubramanian (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Ian Feng, Henry Sun, Shou-Chieh Hsu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58102 ) Change subject: mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f3edb0b594066714b42050a411103a215e68b12 Gerrit-Change-Number: 58102 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 16:07:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support
by Aseda Aboagye (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Ian Feng, Henry Sun, Shou-Chieh Hsu, Karthik Ramasubramanian. Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58102 ) Change subject: mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f3edb0b594066714b42050a411103a215e68b12 Gerrit-Change-Number: 58102 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 15:54:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/trogdor: Add new vaviant quackingstick
by Paul Menzel (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Sheng-Liang Pan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58033 ) Change subject: mb/google/trogdor: Add new vaviant quackingstick ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58033/comment/9da42302_daf16ee0 PS1, Line 7: vaviant > Done Apparently it was not. What happened? -- To view, visit https://review.coreboot.org/c/coreboot/+/58033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8299ddda14eb82103f17f8464a14992aa757afa6 Gerrit-Change-Number: 58033 Gerrit-PatchSet: 4 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 14:10:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2
by Mario Scheithauer (Code Review) 05 Oct '21

05 Oct '21

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58112 ) Change subject: mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2 ...................................................................... mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2 This board have the RTC RX6110SA connected to the I2C2 instead of SMBus as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC only supports the standard speed. Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 23 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/58112/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index be98a15..859f08b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -135,6 +135,12 @@ register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" register "PchTsnGbeSgmiiEnable" = "1" + register "common_soc_config" = "{ + .i2c[2] = { + .speed = I2C_SPEED_STANDARD, + }, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -173,7 +179,22 @@ device pci 15.0 off end # I2C0 device pci 15.1 on end # I2C1 - device pci 15.2 off end # I2C2 + device pci 15.2 on # I2C2 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "bus_speed" = "I2C_SPEED_STANDARD" + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end device pci 15.3 off end # I2C3 device pci 16.0 on end # Management Engine Interface 1 @@ -240,22 +261,7 @@ device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 off end # Intel cAVS/HDA - device pci 1f.4 on # SMBus - # Enable external RTC chip - chip drivers/i2c/rx6110sa - register "bus_speed" = "I2C_SPEED_STANDARD" - register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" - register "user_weekday" = "4" - device i2c 0x32 on end # RTC RX6110 SA - end - end + device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI (flash & TPM) device pci 1f.7 off end # PCH Intel Trace Hub end -- To view, visit https://review.coreboot.org/c/coreboot/+/58112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26 Gerrit-Change-Number: 58112 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/dptf: Add support for PCH methods
by Sumeet R Pawnikar (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57925 to look at the new patch set (#6). Change subject: drivers/intel/dptf: Add support for PCH methods ...................................................................... drivers/intel/dptf: Add support for PCH methods Add various methods support for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h M src/soc/intel/alderlake/dptf.c 3 files changed, 164 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/57925/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/57925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Gerrit-Change-Number: 57925 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Add support for PCH methods
by Sumeet R Pawnikar (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, Felix Held. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57925 ) Change subject: drivers/intel/dptf: Add support for PCH methods ...................................................................... Patch Set 5: (2 comments) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/57925/comment/c1d07e12_0b57b376 PS4, Line 356: write_pkgc_method(); > But this will write out 5 copies of the PKGC Method won't it? Don't you see something in `dmesg` abo […] Yes, you are correct. We do not need to do this inside for loop. Uploaded SSDT output on bug for your reference. File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/57925/comment/a7568d5d_f5564823 PS5, Line 230: acpigen_write_package(1); : acpigen_write_zero(); > Sorry I mean this seems like a separate change. […] As per fsp code reference, we need this change for ESIF shell support. -- To view, visit https://review.coreboot.org/c/coreboot/+/57925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Gerrit-Change-Number: 57925 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Oct 2021 13:52:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/tcss: Optimize USB-C DP flow and code structure
by Derek Huang (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Curtis Chen, Brandon Breitenstein. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Brandon Breitenstein, Patrick Rudolph, Curtis Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57139 to look at the new patch set (#24). Change subject: soc/intel/common/tcss: Optimize USB-C DP flow and code structure ...................................................................... soc/intel/common/tcss: Optimize USB-C DP flow and code structure HPD event may not be ready when configuring TCSS mux for DP, check if any DP device is connected and wait for HPD ready before TCSS configuration. Remove unnecessary dependency on mainboard functions, use generic interface which provides USB-C mux operations. BUG=b:192947843 TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name for Brya. Build coreboot and update your Brya. Boot Brya with USB-C display connected, you should find `HPD ready after %lu ms` and `Port C%zd is configured to DP mode!` in coreboot log. Display should show screen in developer mode or recovery mode. Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 --- M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/tcss.c 2 files changed, 44 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/57139/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 24 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2021