coreboot-gerrit October 2021

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable retimer force power gpio
by Bernardo Perez Priego (Code Review) 05 Oct '21

05 Oct '21

Bernardo Perez Priego has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58113 ) Change subject: mb/intel/adlrvp_m: Enable retimer force power gpio ...................................................................... mb/intel/adlrvp_m: Enable retimer force power gpio Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain to toggle during a switch from DP Alt to TBT Alt modes. Contrary to DS specifying it may be left unconfigured, hence floating, there are instances seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp). Hence configure it to LOW. Branch=none Bug=none Test=Boot to OS, connect TBT dock which enumerates in DP Alt, Login, TBT dock enumerates in TBT Alt Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c --- M src/mainboard/intel/adlrvp/gpio_m.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/58113/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c Gerrit-Change-Number: 58113 Gerrit-PatchSet: 2 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable touchpad
by Bernardo Perez Priego (Code Review) 05 Oct '21

05 Oct '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57863 to look at the new patch set (#3). Change subject: mb/intel/adlrvp_m: Enable touchpad ...................................................................... mb/intel/adlrvp_m: Enable touchpad This changes will include ELAN touchpad to ACPI tables and configure GPIO's. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e --- M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/gpio_m.c 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/57863/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/57863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e Gerrit-Change-Number: 57863 Gerrit-PatchSet: 3 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable retimer force power gpio
by build bot (Jenkins) (Code Review) 05 Oct '21

05 Oct '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58113 ) Change subject: mb/intel/adlrvp_m: Enable retimer force power gpio ...................................................................... Patch Set 1: (2 comments) File src/mainboard/intel/adlrvp/gpio_m.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129815): https://review.coreboot.org/c/coreboot/+/58113/comment/de96136b_2c8d2e49 PS1, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129815): https://review.coreboot.org/c/coreboot/+/58113/comment/06c59065_9edd2e8a PS1, Line 175: PAD_CFG_GPO(GPP_E4, 0, DEEP) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/58113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c Gerrit-Change-Number: 58113 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Oct 2021 18:51:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable retimer force power gpio
by Bernardo Perez Priego (Code Review) 05 Oct '21

05 Oct '21

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58113 ) Change subject: mb/intel/adlrvp_m: Enable retimer force power gpio ...................................................................... mb/intel/adlrvp_m: Enable retimer force power gpio Enable OS to use retimer force power pin. Branch= none Bug= none Test= Boot to OS. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c --- M src/mainboard/intel/adlrvp/gpio_m.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/58113/1 diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 6f0568d..915b549 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -169,7 +169,10 @@ PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE), /* E3 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT) + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + + /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_E4, 0, DEEP) }; void variant_configure_gpio_pads(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/58113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c Gerrit-Change-Number: 58113 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc to src/superio: Fix spelling errors
by Martin Roth (Code Review) 05 Oct '21

05 Oct '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58082 ) Change subject: src/soc to src/superio: Fix spelling errors ...................................................................... src/soc to src/superio: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/fch.c M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fch.c M src/soc/amd/picasso/include/soc/platform_descriptors.h M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/chip.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/cavium/cn81xx/bootblock_custom.S M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/northcluster.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/common/Makefile.inc M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/usb4/Kconfig M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/quark/Kconfig M src/soc/intel/quark/chip.h M src/soc/intel/quark/include/soc/QuarkNcSocId.h M src/soc/intel/quark/reg_access.c M src/soc/intel/quark/spi_debug.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/xeon_sp/util.c M src/soc/mediatek/common/include/soc/eint_event.h M src/soc/mediatek/common/mmu_operations.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/pll.c M src/soc/mediatek/mt8195/pll.c M src/soc/nvidia/tegra124/chip.h M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra210/Kconfig M src/soc/nvidia/tegra210/Makefile.inc M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/include/soc/addressmap.h M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/nvidia/tegra210/sdram.c M src/soc/qualcomm/ipq40xx/gpio.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq806x/gpio.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/spi.c M src/soc/samsung/exynos5250/dmc_init_ddr3.c M src/soc/samsung/exynos5250/include/soc/gpio.h M src/soc/samsung/exynos5420/dmc_init_ddr3.c M src/soc/sifive/fu540/ux00ddr.h M src/southbridge/amd/agesa/hudson/acpi/fch.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/pi/hudson/acpi/fch.asl M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/acpi_tables.c M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_status.c M src/southbridge/intel/lynxpoint/pch.h M src/superio/acpi/pnp_config.asl M src/superio/ite/it8772f/it8772f.h M src/superio/winbond/w83627hf/acpi/superio.asl 75 files changed, 91 insertions(+), 91 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 80ce946..ac79cc9 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -127,7 +127,7 @@ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); } -/* configure the genral purpose PCIe clock outputs according to the devicetree settings */ +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { const struct soc_amd_cezanne_config *cfg = config_of_soc(); diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index e948bca..292cdd8 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -29,7 +29,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 6389830..4fcd3f7 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -22,7 +22,7 @@ uint8_t sq_rx_tune; /* FS/LS Source Impedance Adjustment. Range 0 - 0xF */ uint8_t tx_fsls_tune; - /* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */ + /* HS Transmitter Pre-Emphasis Current Control. Range 0 - 0x3 */ uint8_t tx_pre_emp_amp_tune; /* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */ uint8_t tx_pre_emp_pulse_tune; @@ -99,7 +99,7 @@ * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. * For example, should we need I2C0 and I2C3 have their peripheral - * devices reseted by toggling SCL, use: + * devices reset by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 711091c..44acc81 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -175,7 +175,7 @@ write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); } -/* configure the genral purpose PCIe clock outputs according to the devicetree settings */ +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { const struct soc_amd_picasso_config *cfg = config_of_soc(); diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 28062b6..2ea35a9 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -7,7 +7,7 @@ #include <platform_descriptors.h> #include <FspsUpd.h> -/* These tempory macros apply to emmc0_mode field in FSP_S_CONFIG. +/* These temporary macros apply to emmc0_mode field in FSP_S_CONFIG. * TODO: Remove when official definitions arrive. */ #define SD_DISABLE 0 #define SD_LOW_SPEED 1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 78ce889..f7ea782 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -56,7 +56,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 82c5437..b870bae 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -46,7 +46,7 @@ * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. * For example, should we need I2C0 and I2C3 have their peripheral - * devices reseted by toggling SCL, use: + * devices reset by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d80aeb2..d5231ad 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -400,19 +400,19 @@ reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); /* - * 0x100000 (1MiB) -> low top useable RAM + * 0x100000 (1MiB) -> low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ ram_resource(dev, idx++, (1 * MiB) / KiB, (mem_useable - (1 * MiB)) / KiB); - /* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */ + /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_resource(dev, idx++, mem_useable / KiB, (tom.lo - mem_useable) / KiB); /* If there is memory above 4GiB */ if (high_tom.hi) { - /* 4GiB -> high top useable */ + /* 4GiB -> high top usable */ if (uma_base >= (4ull * GiB)) high_mem_useable = uma_base; else @@ -422,7 +422,7 @@ ram_resource(dev, idx++, (4ull * GiB) / KiB, ((high_mem_useable - (4ull * GiB)) / KiB)); - /* High top useable RAM -> high top RAM */ + /* High top usable RAM -> high top RAM */ if (uma_base >= (4ull * GiB)) { reserved_ram_resource(dev, idx++, uma_base / KiB, uma_size / KiB); diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S index 03d91da..318c4d7 100644 --- a/src/soc/cavium/cn81xx/bootblock_custom.S +++ b/src/soc/cavium/cn81xx/bootblock_custom.S @@ -130,7 +130,7 @@ thunder1_cache_setup: /** * Setup L2 cache to allow secure access to all of the address space - * thunder1 compability list: + * thunder1 compatibility list: * - CN81XX * - CN83XX * - CN88XX diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 82cbad63..81c2432 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -511,7 +511,7 @@ TACK, 1, /* [16:16] IOM Acknowledge bit */ DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ /* display is OFF, clear otherwise */ - Offset(0x70), /* Pyhsical addr is offset 0x70. */ + Offset(0x70), /* Physical addr is offset 0x70. */ IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ } diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 6a71900..f6b337c 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -18,7 +18,7 @@ Offset(0xB4), BGSM, 32, /* Base of Graphics Stolen Memory */ Offset(0xBC), - TLUD, 32, /* Top of Low Useable DRAM */ + TLUD, 32, /* Top of Low Usable DRAM */ } } @@ -58,7 +58,7 @@ * PCI MMIO Region (TOLUD - PCI extended base MMCONF) * This assumes that MMCONF is placed after PCI config space, * and that no resources are allocated after the MMCONF region. - * This works, sicne MMCONF is hardcoded to 0xe00000000. + * This works, since MMCONF is hardcoded to 0xe00000000. */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1c92b89..c4d7977 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -119,7 +119,7 @@ /* * Poll for bit 8 to check if PCODE has completed its action - * in reponse to BIOS Reset complete. + * in response to BIOS Reset complete. * We wait here till 1 ms for the bit to get set. */ stopwatch_init_msecs_expire(&sw, 1); diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index e5c003a..dca95e3 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -136,7 +136,7 @@ bool "Use a binary refcode blob instead of native ModPHY init" default n help - Use the ChromeBook refcode to intitialize high-speed PHYs instead of + Use the ChromeBook refcode to initialize high-speed PHYs instead of native code. if HAVE_REFCODE_BLOB diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index b7ddee4..76d532b5 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -93,7 +93,7 @@ if (fsp_reserved_memory_area) { fsp_res_base_k = RES_IN_KiB((unsigned int)fsp_reserved_memory_area); } else { - /* If no FSP reserverd area */ + /* If no FSP reserved area */ fsp_res_base_k = tseg_base_k; } diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index fbd7aea..f02e810 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -23,7 +23,7 @@ Broadwell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. - Broadwell however uses a mrc.bin to initialse memory which + Broadwell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b8dfafd..774b526 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -436,7 +436,7 @@ * * In general descriptor provides option to set default cpu flex ratio. * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. - * Thats the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. * * Only override CPU flex ratio if don't want to boot with non-turbo max. */ diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 56e3336..ad987dd 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -41,7 +41,7 @@ # $(3) is file type, efi for test names (all .EFI files under $(MMA_BLOBS_PATH)/tests ) # , mma for test param (all .BIN files under $(MMA_BLOBS_PATH)/configs/<test name>) # -# $(MMA_BLOBS_PATH)/tests/<testX>.efi has coresponding test params +# $(MMA_BLOBS_PATH)/tests/<testX>.efi has corresponding test params # at $(MMA_BLOBS_PATH)/configs/<testX>/<XYZ>.bin # diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index f0c3149..cac7854 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -545,7 +545,7 @@ /* * Calculate the SF Mask 1: - * 1. Calcuate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0] + * 1. Calculate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0] * 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: SFWayCnt = SFWayCnt / 2 * 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - IA32_CR_SF_QOS_MASK_2 */ diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 843071e..93de2ec 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -325,7 +325,7 @@ "Only 32MiB windows are supported for extended BIOS!"); #endif - /* Confgiure DMI Source decode for Extended BIOS Region */ + /* Configure DMI Source decode for Extended BIOS Region */ if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, soc_get_spi_dmi_destination_id()) == CB_ERR) return; diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 97d63af..c07c96c 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -130,7 +130,7 @@ struct tcss_mux_info { bool dp; /* DP connected */ bool usb; /* USB connected */ - bool cable; /* Activ/Passive Cable */ + bool cable; /* Active/Passive Cable */ bool polarity; /* polarity of connected device */ bool hpd_lvl; /* HPD Level assert */ bool hpd_irq; /* HPD IRQ assert */ diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index aaf4479..e3978e2 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -17,7 +17,7 @@ bool help Select this on platforms where the PMC device is discoverable - when scanning busses. + when scanning buses. config SOC_INTEL_COMMON_BLOCK_PMC_EPOC bool diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig index d4e1c25..bc1eb19 100644 --- a/src/soc/intel/common/block/usb4/Kconfig +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -25,4 +25,4 @@ depends on SOC_INTEL_COMMON_BLOCK_USB4 select PCIEXP_HOTPLUG help - Enable USB4 PCIe resources for reserving hotplug busses and memory. + Enable USB4 PCIe resources for reserving hotplug buses and memory. diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 512f7f5..fdb1028 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -11,7 +11,7 @@ #define MASK_PMC_ACPI_BASE 0xfffc #define PMC_ACPI_CNT 0x44 #define PMC_ACPI_CNT_PWRM_EN (1 << 8) /* PWRM enable */ -#define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI eanble */ +#define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI enable */ #define PMC_ACPI_CNT_SCIS ((1 << 2) | (1 << 1) | (1 << 0)) /* SCI IRQ select \ */ #define PMC_ACPI_CNT_SCIS_MASK 0x07 diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2d09f51..1a9bfef 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -222,7 +222,7 @@ select COMMONLIB_STORAGE select SDHCI_CONTROLLER help - Read block 0 from each parition of the storage device. User + Read block 0 from each partition of the storage device. User must also enable one or both of COMMONLIB_STORAGE_SD or COMMONLIB_STORAGE_MMC. diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 40e823f..7308712 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -87,7 +87,7 @@ uint8_t DramDensity; uint8_t tCL; /* DRAM CAS Latency in clocks */ - /* ECC scrub interval in miliseconds 1..255 (0 works as feature + /* ECC scrub interval in milliseconds 1..255 (0 works as feature * disable) */ uint8_t EccScrubInterval; diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h index c7db8d5..e4015a2 100644 --- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -55,7 +55,7 @@ // // -// DEVICE 0 (Memroy Controller Hub) +// DEVICE 0 (Memory Controller Hub) // #define MC_BUS PCI_BUS_NUMBER_QNC #define MC_DEV 0x00 @@ -729,7 +729,7 @@ #define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset #define R_QNC_PCIE_SLCTL 0x58 //~ 59h #define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug intr enable -#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect enable +#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presence detect enable #define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attn Btn Pressed Enable #define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh #define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 8671398..604561a 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -69,7 +69,7 @@ { uint32_t offset; - /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */ + /* Convert from MTRR index to host bridge offset (Datasheet 12.7.2) */ if (index == MTRR_CAP_MSR) offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; else if (index == MTRR_DEF_TYPE_MSR) diff --git a/src/soc/intel/quark/spi_debug.c b/src/soc/intel/quark/spi_debug.c index b249065..a6b5e69 100644 --- a/src/soc/intel/quark/spi_debug.c +++ b/src/soc/intel/quark/spi_debug.c @@ -79,7 +79,7 @@ printk(BIOS_DEBUG, "0x%08x: BIOS Base Address\n", ctrlr->bbar); /* Display the protection ranges */ - printk(BIOS_DEBUG, "BIOS Protected Range Regsiters\n"); + printk(BIOS_DEBUG, "BIOS Protected Range Registers\n"); for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) { status = ctrlr->pbr[index]; printk(BIOS_DEBUG, " %d: 0x%08x: 0x%08x - 0x%08x %s\n", diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 7e06ffa..72c5e47 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -36,7 +36,7 @@ #define CPUID_6_EAX_ISST (1 << 7) /* - * List of suported C-states in this processor. + * List of supported C-states in this processor. */ enum { C_STATE_C0, /* 0 */ diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 3d12861..dd28255 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -30,7 +30,7 @@ int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); /* - * Add nau88l25 headset codec on provided SSP link. Return 0 on succes, < 0 + * Add nau88l25 headset codec on provided SSP link. Return 0 on success, < 0 * on error. */ int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink); diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 9893833..2a71b31 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -511,7 +511,7 @@ TACK, 1, /* [16:16] IOM Acknowledge bit */ DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ /* display is OFF, clear otherwise */ - Offset(0x70), /* Pyhsical addr is offset 0x70. */ + Offset(0x70), /* Physical addr is offset 0x70. */ IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ } diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index ce0b1a6..579ebbc 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -168,7 +168,7 @@ unsigned int num_sockets; /* - * sort APIC ids in asending order to identify apicid ranges for + * sort APIC ids in ascending order to identify apicid ranges for * each numa domain */ for (dev = all_devices; dev; dev = dev->next) { diff --git a/src/soc/mediatek/common/include/soc/eint_event.h b/src/soc/mediatek/common/include/soc/eint_event.h index 98db7b0..6d544b4 100644 --- a/src/soc/mediatek/common/include/soc/eint_event.h +++ b/src/soc/mediatek/common/include/soc/eint_event.h @@ -6,7 +6,7 @@ #include <device/mmio.h> #include <soc/addressmap.h> -/* eint event mask cler register */ +/* eint event mask clear register */ struct eint_event_reg { uint32_t eint_event_mask_clr[7]; }; diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index 960d742..340f9ec 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -50,6 +50,6 @@ mtk_soc_disable_l2c_sram(); - /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ + /* Re-enable MMU with now enlarged L2 cache. Page tables still valid. */ mmu_enable(); } diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 009d03a..23a9403 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -777,7 +777,7 @@ * ISI 0 | 0 * AUD 0 | 1 * XTALK 1 | 0 - * UNKNOW 1 | 1 + * UNKNOWN 1 | 1 */ switch (testaudpat) { case XTALK: diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index f0a9509..e49e222 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -524,7 +524,7 @@ SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, CLK_MISC_CFG_0_METER_DIV, 0); } else { - die("unsupport fmeter type\n"); + die("unsupported fmeter type\n"); } /* enable frequency meter */ diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 74dd150..8fd424d 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -844,7 +844,7 @@ SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, CLK_MISC_CFG_0_METER_DIV, 0); } else { - die("unsupport fmeter type\n"); + die("unsupported fmeter type\n"); } /* enable frequency meter */ diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 0d1fb19..bc033c9 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -54,7 +54,7 @@ /* Delay before from power on asserting vdd */ int vdd_delay_ms; - /* Delay beween pwm and backlight_en_gpio is asserted */ + /* Delay between pwm and backlight_en_gpio is asserted */ int pwm_to_bl_delay_ms; /* Delay before HPD high */ diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 4155c34..5da2c06 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -465,7 +465,7 @@ return (cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; } -/* Calcuate if given cfg can meet the mode request. */ +/* Calculate if given cfg can meet the mode request. */ /* Return true if mode is possible, false otherwise. */ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, const struct soc_nvidia_tegra124_config *config, diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 4fcbaff..0244b47 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -79,7 +79,7 @@ default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE help - Map the UART names to the respective MMIO addres. + Map the UART names to the respective MMIO addresses. config BOOTROM_SDRAM_INIT bool "SoC BootROM does SDRAM init with full BCT" diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index f76ab34..5846be9 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -137,7 +137,7 @@ tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1) - $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be atleast as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") + $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be at least as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") endif # BL31 component is placed towards the end of 32-bit address space. This assumes diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index 9c55242..a2b06b1 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -477,7 +477,7 @@ return (link_cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; } -/* Calcuate if given cfg can meet the mode request. */ +/* Calculate if given cfg can meet the mode request. */ /* Return true if mode is possible, false otherwise. */ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, const struct soc_nvidia_tegra210_config *config, diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index 31ed4f2..bd9a25c 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -94,7 +94,7 @@ /* Return total size of DRAM memory configured on the platform. */ int sdram_size_mb(void); -/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */ +/* Find memory below and above 4GiB boundary respectively. All units 1MiB. */ void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib); void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib); diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c index cd1b822..067dc6d 100644 --- a/src/soc/nvidia/tegra210/mipi_dsi.c +++ b/src/soc/nvidia/tegra210/mipi_dsi.c @@ -193,7 +193,7 @@ /* * DCS long write packets contain the word count in the header * bytes 1 and 2 and have a payload containing the DCS command - * byte folowed by word count minus one bytes. + * byte followed by word count minus one bytes. * * DCS short write packets encode the DCS command and up to * one parameter in header bytes 1 and 2. diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index 8ffa0e5..702897f 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -155,7 +155,7 @@ /* * Program CMD mapping. Required before brick mapping, else - * we can't gaurantee CK will be differential at all times. + * we can't guarantee CK will be differential at all times. */ write32(&regs->fbio_cfg7, param->EmcFbioCfg7); @@ -979,7 +979,7 @@ /* Enable EMC pipe clock gating */ write32(&regs->cfg_pipe_clk, param->EmcCfgPipeClk); - /* Depending on freqency, enable CMD/CLK fdpd */ + /* Depending on frequency, enable CMD/CLK fdpd */ write32(&regs->fdpd_ctrl_cmd_no_ramp, param->EmcFdpdCtrlCmdNoRamp); } diff --git a/src/soc/qualcomm/ipq40xx/gpio.c b/src/soc/qualcomm/ipq40xx/gpio.c index e7874a7..8e248c5 100644 --- a/src/soc/qualcomm/ipq40xx/gpio.c +++ b/src/soc/qualcomm/ipq40xx/gpio.c @@ -18,7 +18,7 @@ } /******************************************************* -Function description: configure GPIO functinality +Function description: configure GPIO functionality Arguments : gpio_t gpio - Gpio number unsigned func - Functionality number @@ -77,7 +77,7 @@ } /******************************************************* -Function description: get GPIO IO functinality details +Function description: get GPIO IO functionality details Arguments : gpio_t gpio - Gpio number unsigned *in - Value of GPIO input diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index da7a6d3..31677e4 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -328,7 +328,7 @@ } /* - * Function to check wheather Input or Output FIFO + * Function to check whether Input or Output FIFO * has data to be serviced */ static int check_fifo_status(void *reg_addr) @@ -627,7 +627,7 @@ || ((bus == BLSP0_SPI) && (cs > 2)) || ((bus == BLSP1_SPI) && (cs > 0))) { printk(BIOS_ERR, - "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " + "SPI error: unsupported bus %d (Supported buses 0, 1 and 2) " "or chipselect\n", bus); return -1; } diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index e7874a7..8e248c5 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -18,7 +18,7 @@ } /******************************************************* -Function description: configure GPIO functinality +Function description: configure GPIO functionality Arguments : gpio_t gpio - Gpio number unsigned func - Functionality number @@ -77,7 +77,7 @@ } /******************************************************* -Function description: get GPIO IO functinality details +Function description: get GPIO IO functionality details Arguments : gpio_t gpio - Gpio number unsigned *in - Value of GPIO input diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index ce420af..cce7ed9 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -84,7 +84,7 @@ qup_config = &gsbi7_qup_config; break; default: - printk(BIOS_ERR, "QUP configuration not defind for GSBI%d.\n", + printk(BIOS_ERR, "QUP configuration not defined for GSBI%d.\n", gsbi_id); return 1; } diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 2b18bda..c538c27 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -758,7 +758,7 @@ || ((bus == GSBI6_SPI) && (cs > 0)) || ((bus == GSBI7_SPI) && (cs > 0))) { printk(BIOS_ERR, "SPI error: unsupported bus %d " - "(Supported busses 0,1 and 2) or chipselect\n", bus); + "(Supported buses 0,1 and 2) or chipselect\n", bus); } for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 3a3a8bf..15a0998 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -367,7 +367,7 @@ return byte; } -/* TODO: Implement fuction */ +/* TODO: Implement function */ void uart_fill_lb(void *data) { } diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 4607dc1..e212b84 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -376,7 +376,7 @@ } /* - * Function to check wheather Input or Output FIFO + * Function to check whether Input or Output FIFO * has data to be serviced */ static int check_fifo_status(void *reg_addr) diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index f415020..33725bc 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -124,7 +124,7 @@ if (mem_reset) { /* Send NOP, MRS and ZQINIT commands. * Sending MRS command will reset the DRAM. We should not be - * reseting the DRAM after resume, this will lead to memory + * resetting the DRAM after resume, this will lead to memory * corruption as DRAM content is lost after DRAM reset */ dmc_config_mrs(mem, exynos_dmc); diff --git a/src/soc/samsung/exynos5250/include/soc/gpio.h b/src/soc/samsung/exynos5250/include/soc/gpio.h index 5a58b29..ede70d3 100644 --- a/src/soc/samsung/exynos5250/include/soc/gpio.h +++ b/src/soc/samsung/exynos5250/include/soc/gpio.h @@ -546,7 +546,7 @@ enum mvl3 { LOGIC_0, LOGIC_1, - LOGIC_Z, /* high impedence / tri-stated / floating */ + LOGIC_Z, /* high impedance / tri-stated / floating */ }; #endif /* CPU_SAMSUNG_EXYNOS5250_GPIO_H */ diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index b1eae89..a187f6e 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -147,7 +147,7 @@ if (reset) { /* Send NOP, MRS and ZQINIT commands. * Sending MRS command will reset the DRAM. We should not be - * reseting the DRAM after resume, this will lead to memory + * resetting the DRAM after resume, this will lead to memory * corruption as DRAM content is lost after DRAM reset. */ dmc_config_mrs(mem, exynos_drex0); diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h index 14a628d..cc67508 100644 --- a/src/soc/sifive/fu540/ux00ddr.h +++ b/src/soc/sifive/fu540/ux00ddr.h @@ -82,14 +82,14 @@ static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) { // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status - // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured - // Bit [1] A memory access outside the defined PHYSICAL memory space has occured + // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occurred + // Bit [1] A memory access outside the defined PHYSICAL memory space has occurred _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET)); } static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) { // Mask off Bit 7 of Interrupt Status - // Bit [7] An error occured on the port command channel + // Bit [7] An error occurred on the port command channel _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET); } diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 38f2bca..b87b9e4 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -67,7 +67,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 2059db0..88fbf7b 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -77,7 +77,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 88cf47f..9a2c744 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -50,7 +50,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 1f14c42..3b07a15 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -162,7 +162,7 @@ if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index b4f0c4c..dfebaf0 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -31,7 +31,7 @@ typedef struct southbridge_intel_bd82x6x_config config_t; /** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 7507cd5..41fc4ee 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -29,7 +29,7 @@ int numcpus = determine_total_number_of_cores(); printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus); - /* without the outer scope, furhter ssdt addition will end up + /* without the outer scope, further ssdt addition will end up * within the processor statement */ acpigen_write_scope("\\_SB"); for (cpu=0; cpu < numcpus; cpu++) { diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 988d741..5b9f8be 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -27,7 +27,7 @@ * bit25 (lid_pol): 1=invert lid polarity * bit24 (sm_freeze): 1=freeze idle and standby timers * bit16 (end of smi): 0=disable smi assertion (cleared by hw) - * bits8-15,26: global standby timer inital count 127 * 4minutes + * bits8-15,26: global standby timer initial count 127 * 4minutes * bit2 (thrm_pol): 1=active low THRM# * bit0 (smi_en): 1=disable smi generation upon smi event */ diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 6ff6064..321c605 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -32,7 +32,7 @@ } /** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index fde06b4..0473de6 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -190,7 +190,7 @@ if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)(uintptr_t)base); diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index ff890a2..90d784c 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -183,7 +183,7 @@ if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 5efbc9f..885c332 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -183,7 +183,7 @@ if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index ef781b7..683715f 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -162,7 +162,7 @@ if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 8cc9b42..c14c6a2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -28,7 +28,7 @@ typedef struct southbridge_intel_ibexpeak_config config_t; /** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f3c08d8..d0eb4b3 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -25,7 +25,7 @@ #define NMI_OFF 0 /** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 82a8f8e..fb4490f 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -187,7 +187,7 @@ break; default: - printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x", + printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", hfs2->progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 598c2dc..7d9fc6d 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -647,7 +647,7 @@ #define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET) #define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET) -/* Reigsters within the SPIBAR */ +/* Registers within the SPIBAR */ #define SSFC 0x91 #define FDOC 0xb0 #define FDOD 0xb4 diff --git a/src/superio/acpi/pnp_config.asl b/src/superio/acpi/pnp_config.asl index 0257cc7..7ce8fd5 100644 --- a/src/superio/acpi/pnp_config.asl +++ b/src/superio/acpi/pnp_config.asl @@ -26,7 +26,7 @@ Mutex(CONF_MODE_MUTEX, 1) /* - * Enter configuration mode (and aquire mutex) + * Enter configuration mode (and acquire mutex) * Method must be run before accessing the configuration region. * Parameter is the LDN which should be accessed. Values >= 0xFF mean * no LDN switch should be done. diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 949ec11..38cfe3b 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -103,7 +103,7 @@ /* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ #define GPIO_REG_POLARITY(x) (0xb0 + (x)) -/* GPIO Inernal Pull-up: 1: Enable, 0: Disable */ +/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ #define GPIO_REG_PULLUP(x) (0xb8 + (x)) /* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 5e23cb0..2061030 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -33,10 +33,10 @@ * NO_W83627HF_GAME: don't expose the game port * NO_W83627HF_MIDI: don't expose the MIDI port * NO_W83627HF_HWMON: don't expose the hardware monitor as - * PnP "Motherboard Ressource" + * PnP "Motherboard Resource" * W83627HF_KBC_COMPAT: show the keyboard controller and the PS/2 mouse as * enabled if it is disabled but an address is assigned - * to it. This may be neccessary in some cases. + * to it. This may be necessary in some cases. * * Datasheet: "W83627HF/F WINBOND I/O" rev. 6.0 * http://www.itox.com/pages/support/wdt/W83627HF.pdf @@ -115,14 +115,14 @@ Offset (0x74), DMA0, 8, /* DMA */ Offset (0xE0), - /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ + /* CRE0-CRE4: function logical device dependent, seems to be reserved for ACPI settings */ CRE0, 8, CRE1, 8, CRE2, 8, CRE3, 8, CRE4, 8, Offset (0xF0), - /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ + /* OPT1-OPTA aka CRF0-CRF9: function logical device dependent */ OPT1, 8, OPT2, 8, OPT3, 8, @@ -143,7 +143,7 @@ }) } - /* Enter configuration mode (and aquire mutex) + /* Enter configuration mode (and acquire mutex) Method must be run before accessing the configuration region. Parameter is the LDN which should be accessed. Values >= 0xFF mean no LDN switch should be done. -- To view, visit https://review.coreboot.org/c/coreboot/+/58082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Gerrit-Change-Number: 58082 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp.hug(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/mainboard to src/security: Fix spelling errors
by Martin Roth (Code Review) 05 Oct '21

05 Oct '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58081 ) Change subject: src/mainboard to src/security: Fix spelling errors ...................................................................... src/mainboard to src/security: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/facebook/fbg1701/ramstage.c M src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex M src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex M src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/foster/bct/jtag.cfg M src/mainboard/google/gru/pwm_regulator.c M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/mistral/romstage.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/yorp/gpio.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl M src/mainboard/google/smaug/bct/jtag.cfg M src/mainboard/google/stout/dsdt.asl M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/intel/kblrvp/acpi/mipi_camera.asl M src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c M src/mainboard/lenovo/s230u/acpi/ec.asl M src/mainboard/lippert/frontrunner-af/dsdt.asl M src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex M src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex M src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex M src/mainboard/protectli/vault_bsw/romstage.c M src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl M src/mainboard/roda/rk9/acpi/ec.asl M src/mainboard/roda/rk9/acpi/thermal.asl M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/sandybridge/raminit_common.c M src/security/intel/cbnt/logging.c M src/security/intel/stm/SmmStm.c M src/security/intel/txt/common.c M src/security/memory/memory_clear.c M src/security/tpm/tspi.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h 58 files changed, 64 insertions(+), 64 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 6ecdaf4..c3ba99c 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -127,7 +127,7 @@ .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_OFF" register "gpp_clk_config[1]" = "GPP_CLK_OFF" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 6342c29..167c366 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -118,7 +118,7 @@ .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 035bb70..1bc5498 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -118,7 +118,7 @@ .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 83b6597..93d37dc 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -129,7 +129,7 @@ irq 0xe9 = 0x02 irq 0xf0 = 0x20 end - device pnp 2e.b off end # HWM, front pannel LED + device pnp 2e.b off end # HWM, front panel LED device pnp 2e.d on end # VID device pnp 2e.e off end # CIR WAKE-UP device pnp 2e.f on end # GPIO Push-Pull or Open-drain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index a50c2ac..ff05030 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -105,7 +105,7 @@ irq 0xe9 = 0x02 irq 0xf0 = 0x20 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 io 0x62 = 0x200 irq 0x70 = 0 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 7ceefaa..89e6ebb 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -99,7 +99,7 @@ device pnp 2e.a on # ACPI irq 0xe4 = 0x10 # Power dram during s3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index e583f7f..c3c6b1b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -100,7 +100,7 @@ device pnp 2e.a on # ACPI irq 0xe4 = 0x10 # Power dram during s3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index 48376ff..5efb749 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -34,7 +34,7 @@ irq 0x70 = 0 irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index 78ad877..8653cec 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -106,9 +106,9 @@ { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 1, 0x0080 }, /* USB3 ETH top connector */ - { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 1, 0x0080 }, /* USB3 ETH bottom connector */ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 5f32d8b..387a667 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -18,7 +18,7 @@ * with -bios option which neatly puts coreboot into flash and so payloads * can find CBFS and we don't risk overwriting CBFS. * - * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash + * Prior to Jul 2014 qemu aliased 0 to beginning of RAM instead of flash * and -bios was unusable as $pc pointed to 0 which was zero-filled as a * workaround we suggested using -kernel but this still had all the issues * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index a239590..e972f54 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -2,7 +2,7 @@ /* * These are the qemu firmware config interface defines and structs. - * Copied over from qemu soure tree, + * Copied over from qemu source tree, * include/standard-headers/linux/qemu_fw_cfg.h and modified accordingly. */ #ifndef FW_CFG_IF_H diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 4a9a52f..ec86c70a 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -16,7 +16,7 @@ * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index be99573..cdd34a4 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -181,7 +181,7 @@ {6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00} }, {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} }, {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, - /* Additional Settng for eDP */ + /* Additional Setting for eDP */ {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} }, {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} }, /* DPRX CAD Register Setting */ diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c51a5b901..5a81678 100644 --- a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex index 5007a26..f0dc7fb 100644 --- a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index c3b71d6..2a03e04 100644 --- a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -38,7 +38,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 04 # 5 SDRAM Addressing diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 1df786d..8e2bbe8 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -202,7 +202,7 @@ static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c0(); exynos_pinmux_i2c1(); exynos_pinmux_i2c2(); @@ -222,7 +222,7 @@ gpio_direction_output(GPIO_X17, 1); gpio_direction_output(GPIO_X15, 1); - /* Set up the I2S busses. */ + /* Set up the I2S buses. */ exynos_pinmux_i2s0(); exynos_pinmux_i2s1(); } diff --git a/src/mainboard/google/foster/bct/jtag.cfg b/src/mainboard/google/foster/bct/jtag.cfg index e9bbd02..58186b2 100644 --- a/src/mainboard/google/foster/bct/jtag.cfg +++ b/src/mainboard/google/foster/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set DebugCtrl to 1 to reenable Jtag +# Set DebugCtrl to 1 to re-enable Jtag # DebugCtrl = 0; # diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 5dddab5..3aafa9e 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -60,7 +60,7 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) { int duty_ns, voltage_max, voltage_min; - int voltage = millivolt * 10; /* for higer calculation accuracy */ + int voltage = millivolt * 10; /* for higher calculation accuracy */ int pwm_number = pwm_enum_to_pwm_number[pwm]; voltage_min = pwm_design_voltage[pwm][0]; diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 260e934..381cbaa 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -80,7 +80,7 @@ register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f78d420..a84eabd 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -44,7 +44,7 @@ register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" - # SD card WP pin confguration + # SD card WP pin configuration register "ScsSdCardWpPinEnabled" = "0" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 59c4959..ffec6a5 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -117,7 +117,7 @@ gpios = variant_gpio_table(&num_gpios); gpio_configure_pads(gpios, num_gpios); - /* Initialize i2c busses that were not initialized in bootblock */ + /* Initialize i2c buses that were not initialized in bootblock */ i2c_soc_init(); /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */ diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 1816daf..728487a 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -7,7 +7,7 @@ { /* * Do DWC3 core and phy reset. Kick these resets off early - * so they get atleast 1msec to settle. + * so they get at least 1msec to settle. */ reset_usb(HSUSB_HS_PORT_1); } diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 0e9dc13..afbea9c 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -231,7 +231,7 @@ static void mainboard_init(struct device *dev) { /* TP_SHIFT_EN: Enables the level shifter for I2C bus 4 (TPAD), which - * also contains the PS8640 eDP brige and the USB hub. + * also contains the PS8640 eDP bridge and the USB hub. */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) mt6391_gpio_output(MT6391_KP_ROW2, 1); diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 65bf286..9ffd633 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -69,7 +69,7 @@ /* * Currently we only have the case of RT5682 as the second source. And * in case of Ampton which used RT5682 as the default source, it didn't - * provide override_table right now so it will be returned ealier since + * provide override_table right now so it will be returned earlier since * table above is NULL. */ if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682) diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 85b0cc0..6878cad 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -324,7 +324,7 @@ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index e6b8359..63763b3 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -25,7 +25,7 @@ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index c279777..9cefb81 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -330,7 +330,7 @@ static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c2(); exynos_pinmux_i2c4(); exynos_pinmux_i2c7(); diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 4b1254d..d588d57 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -262,7 +262,7 @@ * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) diff --git a/src/mainboard/google/smaug/bct/jtag.cfg b/src/mainboard/google/smaug/bct/jtag.cfg index 4f2c36c..c48e54a 100644 --- a/src/mainboard/google/smaug/bct/jtag.cfg +++ b/src/mainboard/google/smaug/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set JtagCtrl to 1 to reenable Jtag +# Set JtagCtrl to 1 to re-enable Jtag # JtagCtrl = 0; # diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 8e2d859..89958c9 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -17,7 +17,7 @@ #include "acpi/platform.asl" #include "acpi/mainboard.asl" - // Thermal handeler + // Thermal handler #include "acpi/thermal.asl" // global NVS and variables diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 9476723..68eb6ea 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -21,7 +21,7 @@ }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -232,7 +232,7 @@ register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index ce01215..4bb42de 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -19,7 +19,7 @@ }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -230,7 +230,7 @@ register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_OFF" diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 43ae715..3f7e5d1 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -49,7 +49,7 @@ void variant_pcie_gpio_configure(void); /* Per variant FSP-S initialization, default implementation in baseboard and - * overrideable by the variant. */ + * overridable by the variant. */ void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 389b44e..f7821d0 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -81,7 +81,7 @@ device pnp 4e.609 off end # GPIO6 device pnp 4e.709 off end # GPIO7 device pnp 4e.a on end # ACPI - device pnp 4e.b on # HWM, front pannel LED + device pnp 4e.b on # HWM, front panel LED io 0x60 = 0xa30 io 0x62 = 0 # unused end diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 9b1aeb0..5f945c1 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -129,7 +129,7 @@ irq 0xe4 = 0x10 # Power dram during s3 irq 0xe6 = 0x8c end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0xa00 irq 0x70 = 0 end diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index 26108a2..0d1158d 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -108,7 +108,7 @@ * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) @@ -613,7 +613,7 @@ * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index 4d4b578..3f420c0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -104,7 +104,7 @@ } /** - * @brief Customer Overides Memory Table + * @brief Customer Overrides Memory Table * * Platform Specific Overriding Table allows IBV/OEM to pass in platform * information to AGESA diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 7365d74..22c88e0 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -144,7 +144,7 @@ ^HKEY.MHKQ (0x6040) } - /* Lid openend */ + /* Lid opened */ Method (_Q2A, 0, NotSerialized) { LIDS = 1 diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 5d1e261..e35a70b 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -535,7 +535,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c51a5b901..5a81678 100644 --- a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex index 5007a26..f0dc7fb 100644 --- a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index c3b71d6..2a03e04 100644 --- a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -38,7 +38,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 04 # 5 SDRAM Addressing diff --git a/src/mainboard/protectli/vault_bsw/romstage.c b/src/mainboard/protectli/vault_bsw/romstage.c index 0745352..33519b9 100644 --- a/src/mainboard/protectli/vault_bsw/romstage.c +++ b/src/mainboard/protectli/vault_bsw/romstage.c @@ -12,7 +12,7 @@ void mainboard_after_memory_init(void) { /* - * FSP enables internal UART. Disable it and reenable Super I/O UART to + * FSP enables internal UART. Disable it and re-enable Super I/O UART to * prevent loss of debug information on serial. */ pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0); diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl index 72eaca4..7325562 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl @@ -32,7 +32,7 @@ BIF0, 16, BDCP, 16, // BAT Design Capacity BFCP, 16, // BAT Full Capacity - BRCH, 16, // BAT Rechargable + BRCH, 16, // BAT Rechargeable BDVT, 16, // BAT Design Voltage BIF5, 16, BIF6, 16, diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl index 720f92f..fbe4173 100644 --- a/src/mainboard/roda/rk9/acpi/ec.asl +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -42,7 +42,7 @@ FDDI, 1, // floppy on lpt indicator? LIDC, 1, // LID switch Offset(0xd0), - TCPU, 8, // T_CPU in deg Celcius + TCPU, 8, // T_CPU in deg Celsius Offset(0xd6), /* exact purpose of these three is guessed, but it's something about cooling */ diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index 907edc1..5c29846 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -4,7 +4,7 @@ Scope (\_TZ) { - /* degree Celcius to deci-Kelvin (ACPI temperature unit) */ + /* degree Celsius to deci-Kelvin (ACPI temperature unit) */ Method(C2dK, 1) { Add (2732, Multiply (Arg0, 10), Local0) Return (Local0) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 02799d3..2322097 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -35,7 +35,7 @@ } /* - * TODO: We could determine how many PCIe busses we need in the bar. + * TODO: We could determine how many PCIe buses we need in the bar. * For now, that number is hardcoded to a max of 64. */ static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 51ee320..ac19fcc 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -63,7 +63,7 @@ config CHECK_SLFRCS_ON_RESUME def_bool n help - On some boards it may be neccessary to hard reset early + On some boards it may be necessary to hard reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other boards the check always creates a false positive, diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 6610a3e..241eb43 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -22,7 +22,7 @@ { /* * The QuickPath bus number is the topmost bus number, as per the value - * of the SAD_PCIEXBAR register. The register defaults to 256 busses on + * of the SAD_PCIEXBAR register. The register defaults to 256 buses on * reset. Thus, hardcode the bus number when first setting up PCIEXBAR. */ const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4b5f2b3..9ef491b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2437,7 +2437,7 @@ if (enable_iosav_opt) mchbar_write32(MCMNTS_SPARE, 1); - printram("Aggresive write training:\n"); + printram("Aggressive write training:\n"); for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) { FOR_ALL_POPULATED_CHANNELS { diff --git a/src/security/intel/cbnt/logging.c b/src/security/intel/cbnt/logging.c index 55354b4..514e5ac 100644 --- a/src/security/intel/cbnt/logging.c +++ b/src/security/intel/cbnt/logging.c @@ -123,7 +123,7 @@ LOG("SACM INFO MSR (0x13A) raw: 0x%016llx\n", acm_info.raw); LOG(" NEM status: %u\n", acm_info.nem_enabled); LOG(" TPM type: %s\n", tpm_type[acm_info.tpm_type]); - LOG(" TPM succes: %u\n", acm_info.tpm_success); + LOG(" TPM success: %u\n", acm_info.tpm_success); LOG(" FACB: %u\n", acm_info.facb); LOG(" measured boot: %u\n", acm_info.measured_boot); LOG(" verified boot: %u\n", acm_info.verified_boot); diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index e2fab0c..1ebe77d 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -668,7 +668,7 @@ /* * This function return BIOS STM resource. * Produced by SmmStm. - * Comsumed by SmmMpService when Init. + * Consumed by SmmMpService when Init. * * @return BIOS STM resource */ diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 2b7d926..e3e2f5c 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -150,7 +150,7 @@ } /** - * Validate that the provided ACM is useable on this platform. + * Validate that the provided ACM is usable on this platform. */ static int validate_acm(const void *ptr) { diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 557125d..03c6f8b 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -98,7 +98,7 @@ __func__, (void *)pgtbl, (void *)vmem_addr); } - /* Now clear all useable DRAM */ + /* Now clear all usable DRAM */ memranges_each_entry(r, &mem) { if (range_entry_tag(r) != BM_MEM_RAM) continue; diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index e040d80..ed642c3 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -55,7 +55,7 @@ const char *name); /** - * Issue a TPM_Clear and reenable/reactivate the TPM. + * Issue a TPM_Clear and re-enable/reactivate the TPM. * @return TPM_SUCCESS on success. If not a tpm error is returned */ uint32_t tpm_clear_and_reenable(void); diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index f464fe1..cfa533b 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -273,7 +273,7 @@ uint32_t tlcl_lock_nv_write(uint32_t index) { struct tpm2_response *response; - /* TPM Wll reject attempts to write at non-defined index. */ + /* TPM Will reject attempts to write at non-defined index. */ struct tpm2_nv_write_lock_cmd nv_wl = { .nvIndex = HR_NV_INDEX + index, }; @@ -372,7 +372,7 @@ if (!response) return TPM_E_NO_DEVICE; - /* Map TPM2 retrun codes into common vboot represenation. */ + /* Map TPM2 return codes into common vboot representation. */ switch (response->hdr.tpm_code) { case TPM2_RC_SUCCESS: return TPM_SUCCESS; diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h index ae0b7fd..3ae48eb 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h @@ -28,7 +28,7 @@ * tpm_unmarshal_response * * Given a buffer received from the TPM in response to a certain command, - * deserialize the buffer into the expeced response structure. + * deserialize the buffer into the expected response structure. * * struct tpm2_response is a union of all possible responses. * 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Gerrit-Change-Number: 58081 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: src/acpi to src/lib: Fix spelling errors
by Martin Roth (Code Review) 05 Oct '21

05 Oct '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58080 ) Change subject: src/acpi to src/lib: Fix spelling errors ...................................................................... src/acpi to src/lib: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpi.c M src/acpi/device.c M src/arch/arm/armv7/cpu.S M src/arch/arm64/include/arch/asm.h M src/arch/riscv/fit_payload.c M src/arch/riscv/opensbi.c M src/arch/x86/c_start.S M src/commonlib/bsd/include/commonlib/bsd/compiler.h M src/commonlib/include/commonlib/iobuf.h M src/console/Kconfig M src/cpu/x86/64bit/exit32.inc M src/cpu/x86/pae/pgtbl.c M src/cpu/x86/sipi_vector.S M src/device/Kconfig M src/device/azalia_device.c M src/device/dram/ddr4.c M src/device/oprom/include/x86emu/regs.h M src/device/oprom/x86emu/LICENSE M src/device/oprom/x86emu/prim_ops.c M src/device/pci_early.c M src/device/pnp_device.c M src/device/resource_allocator_v4.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/crb/tpm.c M src/drivers/generic/gpio_keys/chip.h M src/drivers/i2c/lm96000/chip.h M src/drivers/i2c/nct7802y/chip.h M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tpm.c M src/drivers/i2c/ww_ring/ww_ring_programs.c M src/drivers/i2c/ww_ring/ww_ring_programs.h M src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/supermicro_oem.c M src/drivers/net/Kconfig M src/drivers/net/atl1e.c M src/drivers/net/r8168.c M src/drivers/spi/spi_sdcard.c M src/drivers/spi/tpm/tpm.c M src/ec/compal/ene932/acpi/ec.asl M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h M src/ec/google/wilco/commands.h M src/ec/quanta/ene_kb3940q/acpi/ec.asl M src/ec/quanta/it8518/acpi/battery.asl M src/ec/quanta/it8518/acpi/ec.asl M src/include/acpi/acpi.h M src/include/cpu/x86/save_state.h M src/include/device/i2c_simple.h M src/lib/device_tree.c M src/lib/edid.c M src/lib/nhlt.c M src/lib/region_file.c 52 files changed, 68 insertions(+), 68 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2e15ea9..6417ef8 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1937,15 +1937,15 @@ return 2; case TPM2: return 4; - case SSDT: /* ACPI 3.0 upto 6.3: 2 */ + case SSDT: /* ACPI 3.0 up to 6.3: 2 */ return 2; - case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ + case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 up to 6.3: 3 */ return 1; /* TODO Should probably be upgraded to 2 */ case HMAT: /* ACPI 6.4: 2 */ return 2; case DMAR: return 1; - case SLIT: /* ACPI 2.0 upto 6.3: 1 */ + case SLIT: /* ACPI 2.0 up to 6.3: 1 */ return 1; case SPMI: /* IMPI 2.0 */ return 5; @@ -1957,13 +1957,13 @@ return IVRS_FORMAT_MIXED; case DBG2: return 0; - case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */ + case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 up to 6.3: 2 */ return 1; - case RSDT: /* ACPI 1.0 upto 6.3: 1 */ + case RSDT: /* ACPI 1.0 up to 6.3: 1 */ return 1; - case XSDT: /* ACPI 2.0 upto 6.3: 1 */ + case XSDT: /* ACPI 2.0 up to 6.3: 1 */ return 1; - case RSDP: /* ACPI 2.0 upto 6.3: 2 */ + case RSDP: /* ACPI 2.0 up to 6.3: 2 */ return 2; case EINJ: return 1; diff --git a/src/acpi/device.c b/src/acpi/device.c index 4b59990..1df179b 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -139,7 +139,7 @@ /* * Warning: just as with dev_path() this uses a static buffer - * so should not be called mulitple times in one statement + * so should not be called multiple times in one statement */ const char *acpi_device_path(const struct device *dev) { diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index c53119c..bc3ebd9 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -16,7 +16,7 @@ * the LSB of the set field, but the latter contains the LSB of the way field * minus the highest valid set field... such that when you subtract it from a * [way:0:level] field you end up with a [way - 1:highest_set:level] field - * through the magic of double subtraction. It's quite ingenius, really. + * through the magic of double subtraction. It's quite ingenious, really. * Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without * needing to write to memory. * diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index e6246c3..df5952a 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -19,7 +19,7 @@ .size name, .-name /* - * Certain SoCs have an alignment requiremnt for the CPU reset vector. + * Certain SoCs have an alignment requirement for the CPU reset vector. * Align to a 64 byte typical cacheline for now. */ #define CPU_RESET_ENTRY(name) ENTRY_WITH_ALIGN(name, 6) diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index abce57e..f7f4106 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -7,7 +7,7 @@ #include <fit.h> #include <endian.h> -/* Implements a Berkley Boot Loader (BBL) compatible payload loading */ +/* Implements a Berkeley Boot Loader (BBL) compatible payload loading */ #define MAX_KERNEL_SIZE (64*MiB) diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c index e719560..3a738ec 100644 --- a/src/arch/riscv/opensbi.c +++ b/src/arch/riscv/opensbi.c @@ -2,7 +2,7 @@ #include <sbi/fw_dynamic.h> #include <arch/boot.h> -/* DO NOT INLCUDE COREBOOT HEADERS HERE */ +/* DO NOT INCLUDE COREBOOT HEADERS HERE */ void run_opensbi(const int hart_id, const void *fdt, diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index a4a7b28..cb7d504 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -217,7 +217,7 @@ # use iret to jump to a 64-bit offset in a new code segment # iret will pop cs:rip, flags, then ss:rsp mov %ss, %ax # need to push ss.. - push %rax # push ss instuction not valid in x64 mode, + push %rax # push ss instruction not valid in x64 mode, # so use ax push %rsp pushfq diff --git a/src/commonlib/bsd/include/commonlib/bsd/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h index ee2ff88..4dd09bc 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/compiler.h +++ b/src/commonlib/bsd/include/commonlib/bsd/compiler.h @@ -36,7 +36,7 @@ #endif /* This evaluates to the type of the first expression, unless that is constant - in which case it evalutates to the type of the second. This is useful when + in which case it evaluates to the type of the second. This is useful when assigning macro parameters to temporary variables, because that would normally circumvent the special loosened type promotion rules for integer literals. By using this macro, the promotion can happen at the time the diff --git a/src/commonlib/include/commonlib/iobuf.h b/src/commonlib/include/commonlib/iobuf.h index 472b368..0de7d3e 100644 --- a/src/commonlib/include/commonlib/iobuf.h +++ b/src/commonlib/include/commonlib/iobuf.h @@ -81,7 +81,7 @@ /* Out-of-band drain of ibuf by returning pointer to data of specified size. */ const void *ibuf_oob_drain(struct ibuf *ib, size_t sz); -/* Read arbitray data from input buffer. */ +/* Read arbitrary data from input buffer. */ int ibuf_read(struct ibuf *ib, void *data, size_t sz); /* Read big endian fixed size values. */ @@ -125,7 +125,7 @@ /* Fill the buffer out-of-band. The size is accounted for. */ void *obuf_oob_fill(struct obuf *ob, size_t sz); -/* Write arbitray data to output buffer. */ +/* Write arbitrary data to output buffer. */ int obuf_write(struct obuf *ob, const void *data, size_t sz); /* Write big endian fixed size values. */ diff --git a/src/console/Kconfig b/src/console/Kconfig index 4125e18..4c2e768 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -193,7 +193,7 @@ help Send coreboot debug output to a Ethernet console, it works same way as Linux netconsole, packets are received to UDP - port 6666 on IP/MAC specified with options bellow. + port 6666 on IP/MAC specified with options below. Use following netcat command: nc -u -l -p 6666 config CONSOLE_NE2K_DST_MAC diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 91cccb5..4d1149e 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * For droping from long mode to protected mode. + * For dropping from long mode to protected mode. * * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2", * Document 24593-Rev. 3.31-July 2019 Chapter 5.3 @@ -47,7 +47,7 @@ # use iret to jump to a 32-bit offset in a new code segment # iret will pop cs:rip, flags, then ss:rsp - mov %ss, %ax # need to push ss, but push ss instuction + mov %ss, %ax # need to push ss, but push ss instruction push %rax # not valid in x64 mode, so use ax push %rdx # the rsp to load pushfq # push rflags diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 814dbf5..c8783d6 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -104,7 +104,7 @@ * Use PAE to map a page and then memset it with the pattern specified. * In order to use PAE pagetables for virtual addressing are set up and reloaded * on a 2MiB boundary. After the function is done, virtual addressing mode is - * disabled again. The PAT are set to all cachable, but MTRRs still apply. + * disabled again. The PAT are set to all cacheable, but MTRRs still apply. * * Requires a scratch memory for pagetables and a virtual address for * non identity mapped memory. @@ -124,7 +124,7 @@ * Content at physical address isn't preserved. * @param length The length of the memory segment to memset * @param dest Physical memory address to memset - * @param pat The pattern to write to the pyhsical memory + * @param pat The pattern to write to the physical memory * @return 0 on success, 1 on error */ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl, diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 44b772b..496fd34 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -57,7 +57,7 @@ movw %cs, %ax movw %ax, %ds - /* The gdtaddr needs to be releative to the data segment in order + /* The gdtaddr needs to be relative to the data segment in order * to properly dereference it. The .text section comes first in an * rmodule so _start can be used as a proxy for the load address. */ movl $(gdtaddr), %ebx diff --git a/src/device/Kconfig b/src/device/Kconfig index 5ae3466..ea3e241 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -166,7 +166,7 @@ def_bool n depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM help - Always uncondtionally run the option regardless of other + Always unconditionally run the option regardless of other policies. config ON_DEVICE_ROM_LOAD diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 9202f72..70f8348 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -289,7 +289,7 @@ if (!res) return; - // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // NOTE this will break as soon as the azalia_audio gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base); diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 83beeaf..c5a8d13 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -205,7 +205,7 @@ /* Verify CRC of blocks that have them, do not step over 'used' length */ for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) { - /* this block is not checksumed */ + /* this block is not checksummed */ if (spd_blocks[i].crc_start == 0) continue; /* we shouldn't have this block */ diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index 7640c78..52f599d 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -54,7 +54,7 @@ * EAX & 0xff === AL * EAX & 0xffff == AX * - * etc. The result is that alot of the calculations can then be + * etc. The result is that a lot of the calculations can then be * done using the native instruction set fully. */ diff --git a/src/device/oprom/x86emu/LICENSE b/src/device/oprom/x86emu/LICENSE index f13d418..f1c26cc 100644 --- a/src/device/oprom/x86emu/LICENSE +++ b/src/device/oprom/x86emu/LICENSE @@ -1,7 +1,7 @@ License information ------------------- -The x86emu library is under a BSD style license, comaptible +The x86emu library is under a BSD style license, compatible with the XFree86 and X licenses used by XFree86. The original x86emu libraries were under the GNU General Public License. Due to license incompatibilities between the GPL diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index d794ecb..2350ac1 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -2458,7 +2458,7 @@ switch (feature) { case 0: /* Regardless if we have real data from the hardware, the emulator - * will only support upto feature 1, which we set in register EAX. + * will only support up to feature 1, which we set in register EAX. * Registers EBX:EDX:ECX contain a string identifying the CPU. */ M.x86.R_EAX = 1; diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 3a4d2e0..590b170 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -104,7 +104,7 @@ } /* FIXME: A lot of issues using the following, please avoid. - * Assumes 256 PCI busses, scans them all even when PCI bridges are still + * Assumes 256 PCI buses, scans them all even when PCI bridges are still * disabled. Probes all functions even if 0 is not present. */ pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 699007d..88072b9 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -238,7 +238,7 @@ resource->limit = (1 << (bit + 1)) - 1; /* The block of ones in the mask is expected to be continuous. - If there is any zero inbetween the block of ones, it is ignored + If there is any zero in between the block of ones, it is ignored in the calculation of the resource size and limit. */ if (mask != (resource->limit ^ (resource->size - 1))) printk(BIOS_WARNING, diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index b94c295..6f8159e 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -637,7 +637,7 @@ * order to accomplish best fit for the resources, a list of ranges is maintained by each * resource type (i/o and mem). Domain does not differentiate between mem and prefmem. Since * they are allocated space from the same window, the resource allocator at the domain level - * ensures that the biggest requirement is selected indepedent of the prefetch type. Once the + * ensures that the biggest requirement is selected independent of the prefetch type. Once the * resource allocation for all immediate downstream devices is complete at the domain level, * resource allocator walks down the subtree for each downstream bridge to continue the * allocation process at the bridge level. Since bridges have separate windows for i/o, mem and diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 1e15eda..0d678d1 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -5,7 +5,7 @@ * * $Workfile:: cache_as_ram.S * - * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier + * Description: cache_as_ram.S - AGESA Module Entry Point for GCC compiler * ****************************************************************************** */ diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index fcefe96..9c8f249 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -6,7 +6,7 @@ * * TPM starts in IDLE Mode * - * IDLE --> READY --> Command Receiption + * IDLE --> READY --> Command Reception * ^ | * | v -- Cmd Complete <-- Command Execution diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index 88dfe2e..01f4a12 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -81,7 +81,7 @@ struct acpi_gpio gpio; /* Is this a polled GPIO button? - Optional */ bool is_polled; - /* Poll inverval - Mandatory only if GPIO is polled. */ + /* Poll interval - Mandatory only if GPIO is polled. */ uint32_t poll_interval; /* Details about the key - Mandatory */ struct key_info key; diff --git a/src/drivers/i2c/lm96000/chip.h b/src/drivers/i2c/lm96000/chip.h index 128d1ec..bb86f4e 100644 --- a/src/drivers/i2c/lm96000/chip.h +++ b/src/drivers/i2c/lm96000/chip.h @@ -90,7 +90,7 @@ enum { /* turn fan off below `low_temp - hysteresis` */ LM96000_LOW_TEMP_OFF = 0, - /* keep PWM at mininum duty cycle */ + /* keep PWM at minimum duty cycle */ LM96000_LOW_TEMP_MIN = 1, } min_off; u8 hysteresis; diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h index 03c464a..c4a767d 100644 --- a/src/drivers/i2c/nct7802y/chip.h +++ b/src/drivers/i2c/nct7802y/chip.h @@ -37,7 +37,7 @@ enum nct7802y_fan_smartmode { SMART_FAN_DUTY = 0, /* Target values given in duty cycle %. */ - SMART_FAN_RPM, /* Target valuse given in RPM. */ + SMART_FAN_RPM, /* Target values given in RPM. */ }; enum nct7802y_fan_speed { diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 8e12d1f..a8a310f 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -3,7 +3,7 @@ /* Based on Linux Kernel TPM driver */ /* - * cr50 is a TPM 2.0 capable device that requries special + * cr50 is a TPM 2.0 capable device that requires special * handling for the I2C interface. * * - Use an interrupt for transaction status instead of hardcoded delays diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index ee23ea7..b96099c 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -35,7 +35,7 @@ /* max. number of iterations after I2C NAK for 'long' commands * we need this especially for sending TPM_READY, since the cleanup after the - * transtion to the ready state may take some time, but it is unpredictable + * transition to the ready state may take some time, but it is unpredictable * how long it will take. */ #define MAX_COUNT_LONG 50 diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index 7576a3b..73dd4da 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -91,7 +91,7 @@ * * When solid patterns are deployed with instanteneous color intensity * changes, all three LEDs can be controlled by one engine in sequential - * accesses. But the controllers still neeed to be synchronized. + * accesses. But the controllers still need to be synchronized. * * The maximum timer duration of lp55231 is .48 seconds. To achieve longer * blinking intervals the loops delays are deployed. Only the first controller diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index 4f93651..47d1c77 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -21,7 +21,7 @@ #include <stdint.h> #include "drivers/i2c/ww_ring/ww_ring.h" -/* There are threee independent engines/cores in the controller. */ +/* There are three independent engines/cores in the controller. */ #define LP55231_NUM_OF_ENGINES 3 /* Number of lp55321 controllers on the ring */ @@ -29,7 +29,7 @@ /* * Structure to describe an lp55231 program: pointer to the text of the - * program, its size and load address (load addr + size sould not exceed + * program, its size and load address (load addr + size should not exceed * LP55231_MAX_PROG_SIZE), and start addresses for all of the three * engines. */ diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 976df1c..31ac6c0 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -525,7 +525,7 @@ if (prod_info.product_name != NULL) printk(BIOS_DEBUG, "product name: %s\n", prod_info.product_name); if (prod_info.product_partnumber != NULL) - printk(BIOS_DEBUG, "product part numer: %s\n", prod_info.product_partnumber); + printk(BIOS_DEBUG, "product part number: %s\n", prod_info.product_partnumber); if (prod_info.product_version != NULL) printk(BIOS_DEBUG, "product version: %s\n", prod_info.product_version); if (prod_info.serial_number != NULL) diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c index 87b7fe2..9d5ffc7 100644 --- a/src/drivers/ipmi/supermicro_oem.c +++ b/src/drivers/ipmi/supermicro_oem.c @@ -26,7 +26,7 @@ int ret; size_t i; - /* Only 8 charactars are visible in UI. Cut of on first dash */ + /* Only 8 characters are visible in UI. Cut of on first dash */ for (i = 0; i < 15; i++) { if (coreboot_ver[i] == '-') break; diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig index 282075b..7e111f6 100644 --- a/src/drivers/net/Kconfig +++ b/src/drivers/net/Kconfig @@ -33,7 +33,7 @@ select REALTEK_8168_RESET help This is to set a customized LED mode to distinguish 10/100/1000 - link and speed status with limited LEDs avaiable on a board. + link and speed status with limited LEDs available on a board. Please refer to RTL811x datasheet section 7.2 Customizable LED Configuration for details. With this flag enabled, the customized_leds variable will be read from devicetree setting. diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 9b1b2ab..97ad140 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -127,7 +127,7 @@ /* Check if the base is invalid */ if (!mem_base) { - printk(BIOS_ERR, "atl1e: Error cant find MEM resource\n"); + printk(BIOS_ERR, "atl1e: Error can't find MEM resource\n"); return; } /* Enable but do not set bus master */ diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 398b15d..1fd6edd 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -280,7 +280,7 @@ /* Check if the base is invalid */ if (!io_base) { - printk(BIOS_ERR, "r8168: Error cant find IO resource\n"); + printk(BIOS_ERR, "r8168: Error can't find IO resource\n"); return; } /* Enable but do not set bus master */ diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c index a670111..0a18953 100644 --- a/src/drivers/spi/spi_sdcard.c +++ b/src/drivers/spi/spi_sdcard.c @@ -683,7 +683,7 @@ spi_sdcard_sendbyte(card, 0xff & (c >> 8)); spi_sdcard_sendbyte(card, 0xff & (c >> 0)); - /* recevie and verify data response token */ + /* receive and verify data response token */ c = spi_sdcard_recvbyte(card); if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) { spi_sdcard_disable_cs(card); @@ -742,7 +742,7 @@ spi_sdcard_sendbyte(card, 0xff & (c >> 8)); spi_sdcard_sendbyte(card, 0xff & (c >> 0)); - /* recevie and verify data response token */ + /* receive and verify data response token */ c = spi_sdcard_recvbyte(card); if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) break; diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 1ad1eaa..30b1876 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -3,7 +3,7 @@ * * It assumes that the required SPI interface has been initialized before the * driver is started. A 'sruct spi_slave' pointer passed at initialization is - * used to direct traffic to the correct SPI interface. This dirver does not + * used to direct traffic to the correct SPI interface. This driver does not * provide a way to instantiate multiple TPM devices. Also, to keep things * simple, the driver unconditionally uses of TPM locality zero. * @@ -159,7 +159,7 @@ /* * The first byte of the frame header encodes the transaction type - * (read or write) and transfer size (set to lentgh - 1), limited to + * (read or write) and transfer size (set to length - 1), limited to * 64 bytes. */ header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1); @@ -188,7 +188,7 @@ * the last clock of the byte) is set to 1. * * Due to some SPI controllers' shortcomings (Rockchip comes to - * mind...) we trasmit the 4 byte header without checking the byte + * mind...) we transmit the 4 byte header without checking the byte * transmitted by the TPM during the transaction's last byte. * * We know that cr50 is guaranteed to set the flow control bit to 0 diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index f3fb997..3242cce 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -118,7 +118,7 @@ SWTO, 1, // SW Throttling (1=Active) ; AEh.6 TTHR, 1, // HW (THRM#) Throttling (1=Active) ; AEh.7 TTHM, 1, // TS_THERMAL(1:Throttling for thermal) ; AFh.0 - THTL, 1, // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1 + THTL, 1, // THROTTLING(1:Ctrl H/W throttling act); AFh.1 , 2, // Reserved ; AFh.2-3 NPST, 4, // Number of P-State level ; AFh.4-7 CTMP, 8, // Current CPU Temperature ; B0h diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index ed9f4e4..743651b 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -161,7 +161,7 @@ crosec_io_t crosec_io, void *context); /** - * Performs light verification of the EC<->AP communcation channel. + * Performs light verification of the EC<->AP communication channel. * * @return 0 on success, -1 on error */ @@ -330,7 +330,7 @@ * Get role-based capabilities for a USB-PD port * * @param port Which port to get information about - * @param *power_role_cap The power-role capabillity of the port + * @param *power_role_cap The power-role capability of the port * @param *try_power_role_cap The Try-power-role capability of the port * @param *data_role_cap The data role capability of the port * @param *port_location Location of the port on the device diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index e8b028f..bbe34be 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -2856,7 +2856,7 @@ */ struct __ec_todo_unpacked { /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. - * kb_wake_angle: angle to wakup AP. + * kb_wake_angle: angle to wake up AP. */ int16_t data; } kb_wake_angle; diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index a216345..b70f949 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -10,7 +10,7 @@ KB_POWER_SMI = 0x04, /* Read but do not clear power state information */ KB_POWER_STATUS = 0x05, - /* Inform the EC aboout the reason host is turning off */ + /* Inform the EC about the reason host is turning off */ KB_POWER_OFF = 0x08, /* Control wireless radios */ KB_RADIO_CONTROL = 0x2b, diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 9d8cc28..a14c737 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -75,7 +75,7 @@ KBID, 1, // 0=EN KBD, 1=JP KBD ; 80h.1 , 6, // Reserved ; 80h.2-7 NPST, 8, // Number of P-State level ; 81h - MPST, 8, // Maxumum P-State ; 82h + MPST, 8, // Maximum P-State ; 82h KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; 83h.0 TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; 83h.1 , 1, // Reserved ; 83h.2 diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl index 79a1da3..768f2b1 100644 --- a/src/ec/quanta/it8518/acpi/battery.asl +++ b/src/ec/quanta/it8518/acpi/battery.asl @@ -23,7 +23,7 @@ 0, // 0: Power Unit 0xFFFFFFFF, // 1: Design Capacity 0xFFFFFFFF, // 2: Last Full Charge Capacity - 1, // 3: Battery Technology(Rechargable) + 1, // 3: Battery Technology(Rechargeable) 10800, // 4: Design Voltage 10.8V 0, // 5: Design capacity of warning 0, // 6: Design capacity of low diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index 093593c..36f966f 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -444,7 +444,7 @@ MBTH, 4, // bit 3-0: battery 0 highest level SBTH, 4, // bit 7-4: battery 1 highest level // note: if highest level is 0 or 0xF, it means not defined - // (in this case, use default hightest level, it is 6) + // (in this case, use default highest level, it is 6) Offset(0xEF), // [EC Function Specification Major Version] Offset(0xF0), // [Build ID]~ offset:0F7h diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 01d10c2..2c9af3a 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1267,7 +1267,7 @@ * proximimity domain for the memory. */ int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory); -/* Create Heterogenous Memory Attribute Table */ +/* Create Heterogeneous Memory Attribute Table */ void acpi_create_hmat(acpi_hmat_t *hmat, unsigned long (*acpi_fill_hmat)(unsigned long current)); diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h index d6fcf63..139a5fa 100644 --- a/src/include/cpu/x86/save_state.h +++ b/src/include/cpu/x86/save_state.h @@ -26,7 +26,7 @@ /* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */ int get_apmc_node(u8 cmd); -/* Return -1 on failure, 0 on succes. +/* Return -1 on failure, 0 on success. Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */ int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length); int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length); diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index de1c0eb..8f389b3 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -35,7 +35,7 @@ /* * software_i2c is supposed to be a debug feature. It's usually not compiled in, - * but when it is it can be dynamically enabled at runtime for certain busses. + * but when it is it can be dynamically enabled at runtime for certain buses. * Need this ugly stub to arbitrate since I2C device drivers hardcode * 'i2c_transfer()' as their entry point. */ diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 1fd8874..3821e5c 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -758,7 +758,7 @@ } /* - * Find the next compatible child of a given parent. All children upto the + * Find the next compatible child of a given parent. All children up to the * child passed in by caller are ignored. If child is NULL, it considers all the * children to find the first child which is compatible. * diff --git a/src/lib/edid.c b/src/lib/edid.c index cd7a47a..55876e8 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -433,7 +433,7 @@ /* * Slightly weird to return a global, but I've never - * seen any EDID block wth two range descriptors, so + * seen any EDID block with two range descriptors, so * it's harmless. */ return 1; @@ -481,7 +481,7 @@ We have no samples between those values, so put a threshold at 95000 kHz. If we get anything over 95000 kHz with single channel, we can make this - more sofisticated but it's currently not needed. + more sophisticated but it's currently not needed. */ out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000); extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); @@ -1094,7 +1094,7 @@ } /* - * Given a raw edid bloc, decode it into a form + * Given a raw edid block, decode it into a form * that other parts of coreboot can use -- mainly * graphics bringup functions. The raw block is * required to be 128 bytes long, per the standard, diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 90a6cd9..a061b82 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -126,7 +126,7 @@ wave->channel_mask = speaker_mask; memcpy(&wave->sub_format, &pcm_subformat, sizeof(wave->sub_format)); - /* Calculate the dervied fields. */ + /* Calculate the derived fields. */ wave->block_align = wave->num_channels * wave->bits_per_sample / 8; wave->bytes_per_second = wave->block_align * wave->samples_per_second; diff --git a/src/lib/region_file.c b/src/lib/region_file.c index 4fe91b6..f3e66bf 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -9,7 +9,7 @@ * A region file provides generic support for appending new data * within a storage region. The book keeping is tracked in metadata * blocks where an offset pointer points to the last byte of a newly - * allocated byte sequence. Thus, by taking 2 block offets one can + * allocated byte sequence. Thus, by taking 2 block offsets one can * determine start and size of the latest update. The data does not * have to be the same consistent size, but the data size has be small * enough to fit a metadata block and one data write within the region. -- To view, visit https://review.coreboot.org/c/coreboot/+/58080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Gerrit-Change-Number: 58080 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp.hug(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Documentation: Fix spelling errors
by Martin Roth (Code Review) 05 Oct '21

05 Oct '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58078 ) Change subject: Documentation: Fix spelling errors ...................................................................... Documentation: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/RFC/chip.tex M Documentation/acpi/devicetree.md M Documentation/arch/x86/index.md M Documentation/conf.py M Documentation/contributing/coding_style.md M Documentation/contributing/project_ideas.md M Documentation/drivers/index.md M Documentation/flash_tutorial/index.md M Documentation/gcov.txt M Documentation/getting_started/architecture.md M Documentation/getting_started/writing_documentation.md M Documentation/lib/payloads/fit.md M Documentation/lib/timestamp.md M Documentation/mainboard/amd/padmelon/padmelon.md M Documentation/mainboard/emulation/qemu-aarch64.md M Documentation/mainboard/lenovo/Ivy_Bridge_series.md M Documentation/mainboard/lenovo/Sandy_Bridge_series.md M Documentation/mainboard/lenovo/vboot.md M Documentation/mainboard/ocp/tiogapass.md M Documentation/mainboard/up/squared/index.md M Documentation/northbridge/intel/sandybridge/nri.md M Documentation/northbridge/intel/sandybridge/nri_freq.md M Documentation/northbridge/intel/sandybridge/nri_registers.md M Documentation/releases/coreboot-4.13-relnotes.md M Documentation/releases/coreboot-4.3-relnotes.md M Documentation/security/intel/txt.md M Documentation/security/smm.md M Documentation/security/vboot/measured_boot.md M Documentation/soc/cavium/cn81xx/index.md M Documentation/superio/common/ssdt.md M Documentation/superio/nuvoton/npcd378.md M Documentation/technotes/2020-03-unit-testing-coreboot.md M Documentation/tutorial/part1.md M Documentation/util.md 34 files changed, 42 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/Documentation/RFC/chip.tex b/Documentation/RFC/chip.tex index 01f40c1..c671092 100644 --- a/Documentation/RFC/chip.tex +++ b/Documentation/RFC/chip.tex @@ -7,7 +7,7 @@ \section{Scope} This document defines how LinuxBIOS programmers can specify chips that -are used, specified, and initalized. The current scope is for superio +are used, specified, and initialized. The current scope is for superio chips, but the architecture should allow for specification of other chips such as southbridges. Multiple chips of same or different type are supported. diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md index 5cbaf15..41f5901 100644 --- a/Documentation/acpi/devicetree.md +++ b/Documentation/acpi/devicetree.md @@ -5,7 +5,7 @@ ACPI exposes a platform-independent interface for operating systems to perform power management and other platform-level functions. Some operating systems also use ACPI to enumerate devices that are not immediately discoverable, such -as those behind I2C or SPI busses (in contrast to PCI). This document discusses +as those behind I2C or SPI buses (in contrast to PCI). This document discusses the way that coreboot uses the concept of a "device tree" to generate ACPI tables for usage by the operating system. diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 0e14115..a30c5e2 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -92,6 +92,6 @@ page tables in ROM will be loaded and used, which breaks code and data as the page table doesn't contain the expected data. This in turn leads to undefined behaviour whenever the 'wrong' address is being read. -* Disabling paging in compability mode crashes the CPU. -* Returning from long mode to compability mode crashes the CPU. +* Disabling paging in compatibility mode crashes the CPU. +* Returning from long mode to compatibility mode crashes the CPU. * Entering long mode crashes on AMD host platforms. diff --git a/Documentation/conf.py b/Documentation/conf.py index 3180fd9..70b189a 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -185,7 +185,7 @@ enable_auto_toc_tree = True class MyCommonMarkParser(CommonMarkParser): - # remove this hack once upsteam RecommonMark supports inline code + # remove this hack once upstream RecommonMark supports inline code def visit_code(self, mdnode): from docutils import nodes n = nodes.literal(mdnode.literal, mdnode.literal) diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md index a8c7356..4980659 100644 --- a/Documentation/contributing/coding_style.md +++ b/Documentation/contributing/coding_style.md @@ -801,7 +801,7 @@ A reasonable rule of thumb is to not put inline at functions that have more than 3 lines of code in them. An exception to this rule are the -cases where a parameter is known to be a compiletime constant, and as a +cases where a parameter is known to be a compile time constant, and as a result of this constantness you *know* the compiler will be able to optimize most of your function away at compile time. For a good example of this later case, see the kmalloc() inline function. diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 2f6f738..75c78ca 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -202,9 +202,9 @@ and libraries, consisting of a backend, a frontend and client side scripts. The backend should connect to an SQL database with can be controlled using a RESTful API. The RESTful API should have basic authentication -for managment tasks and new board status uploads. +for management tasks and new board status uploads. -At least one older test result should be keept in the database. +At least one older test result should be kept in the database. The frontend should use established UI libraries or frameworks (for example Angular) to display the current board status, that is if it's working or not diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 40d747d..1b8539d 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -2,7 +2,7 @@ The drivers can be found in `src/drivers`. They are intended for onboard and plugin devices, significantly reducing integration complexity and -they allow to easily reuse existing code accross platforms. +they allow to easily reuse existing code across platforms. * [Intel DPTF](dptf.md) * [IPMI KCS](ipmi_kcs.md) diff --git a/Documentation/flash_tutorial/index.md b/Documentation/flash_tutorial/index.md index 4338297..da3d7f0 100644 --- a/Documentation/flash_tutorial/index.md +++ b/Documentation/flash_tutorial/index.md @@ -7,7 +7,7 @@ ## Contents -* [Flashing internaly](int_flashrom.md) +* [Flashing internally](int_flashrom.md) * [Flashing firmware standalone](ext_standalone.md) * [Flashing firmware externally supplying direct power](ext_power.md) * [Flashing firmware externally without supplying direct power](no_ext_power.md) diff --git a/Documentation/gcov.txt b/Documentation/gcov.txt index 896ec93..750e883 100644 --- a/Documentation/gcov.txt +++ b/Documentation/gcov.txt @@ -19,7 +19,7 @@ +#define BITS_PER_UNIT 8 +#define LONG_LONG_TYPE_SIZE 64 + -+/* There are many gcc_assertions. Set the vaule to 1 if we want a warning ++/* There are many gcc_assertions. Set the value to 1 if we want a warning + message if the assertion fails. */ +#ifndef ENABLE_ASSERT_CHECKING +#define ENABLE_ASSERT_CHECKING 1 diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md index 8d63ac2..09fb960 100644 --- a/Documentation/getting_started/architecture.md +++ b/Documentation/getting_started/architecture.md @@ -41,7 +41,7 @@ ### Cache-As-Ram The *Cache-As-Ram*, also called Non-Eviction mode, or *CAR* allows to use the -CPU cache like regular SRAM. This is particullary usefull for high level +CPU cache like regular SRAM. This is particullary useful for high level languages like `C`, which need RAM for heap and stack. The CAR needs to be activated using vendor specific CPU instructions. @@ -85,7 +85,7 @@ * CPU init (like set up SMM) After initialization tables are written to inform the payload or operating system -about the current hardware existance and state. That includes: +about the current hardware existence and state. That includes: * ACPI tables (x86 specific) * SMBIOS tables (x86 specific) diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index 384fc6d..480ad78 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -6,7 +6,7 @@ That said please always try to write documentation! One problem in the firmware development is the missing documentation. In this document you will get a brief introduction how to write, submit and publish -documenation to coreboot. +documentation to coreboot. ## Preparations diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index ef5e892..ac3c183 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -25,7 +25,7 @@ ## Architecture specifics -The FIT parser needs architecure support. +The FIT parser needs architecture support. ### aarch32 The source code can be found in `src/arch/arm/fit_payload.c`. diff --git a/Documentation/lib/timestamp.md b/Documentation/lib/timestamp.md index d5dc8fa..a769f99 100644 --- a/Documentation/lib/timestamp.md +++ b/Documentation/lib/timestamp.md @@ -99,7 +99,7 @@ ### entries -This field holds the details of each timestamp entry, upto a maximum +This field holds the details of each timestamp entry, up to a maximum of `MAX_TIMESTAMP_CACHE` which is defined as 16 entries. Each entry is defined by: diff --git a/Documentation/mainboard/amd/padmelon/padmelon.md b/Documentation/mainboard/amd/padmelon/padmelon.md index 20b1b13..975426d 100644 --- a/Documentation/mainboard/amd/padmelon/padmelon.md +++ b/Documentation/mainboard/amd/padmelon/padmelon.md @@ -43,7 +43,7 @@ +---------------------+--------------------+ | Size | 8 MiB | +---------------------+--------------------+ -| Flash programing | dediprog header | +| Flash programming | dediprog header | +---------------------+--------------------+ | Package | SOIC-8 | +---------------------+--------------------+ diff --git a/Documentation/mainboard/emulation/qemu-aarch64.md b/Documentation/mainboard/emulation/qemu-aarch64.md index 4df36a9..6db8cef 100644 --- a/Documentation/mainboard/emulation/qemu-aarch64.md +++ b/Documentation/mainboard/emulation/qemu-aarch64.md @@ -1,5 +1,5 @@ # QEMU AArch64 emulator -This page discribes how to build and run coreboot for QEMU/AArch64. +This page describes how to build and run coreboot for QEMU/AArch64. You can use LinuxBoot via `make menuconfig` or an arbitrary FIT image as a payload for QEMU/AArch64. diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index 0f3e4c3..ca02b3c 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -76,7 +76,7 @@ [fl]: flashlayout_Ivy_Bridge.svg -## Reducing Intel Managment Engine firmware size +## Reducing Intel Management Engine firmware size It is possible to reduce the Intel ME firmware size to free additional space for the `bios` region. This is usually referred to as *cleaning the ME* or diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 84bae40..e1d9c77 100644 --- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -48,7 +48,7 @@ [fl]: flashlayout_Sandy_Bridge.svg -## Reducing Intel Managment Engine firmware size +## Reducing Intel Management Engine firmware size It is possible to reduce the Intel ME firmware size to free additional space for the `bios` region. This is usually referred to as *cleaning the ME* or diff --git a/Documentation/mainboard/lenovo/vboot.md b/Documentation/mainboard/lenovo/vboot.md index 3f15360..0a451ab 100644 --- a/Documentation/mainboard/lenovo/vboot.md +++ b/Documentation/mainboard/lenovo/vboot.md @@ -28,7 +28,7 @@ ## 8 MiB ROM limitation *Lenovo* devices with 8 MiB ROM only have a `RO`+`A` partition enabled in the -default FMAP. They are missing the `B` partition, due to size constaints. +default FMAP. They are missing the `B` partition, due to size constraints. You can still provide your own FMAP if you need `RO`+`A`+`B` partitions. ## CMOS diff --git a/Documentation/mainboard/ocp/tiogapass.md b/Documentation/mainboard/ocp/tiogapass.md index 6d6afb1..8c49923 100644 --- a/Documentation/mainboard/ocp/tiogapass.md +++ b/Documentation/mainboard/ocp/tiogapass.md @@ -51,7 +51,7 @@ ## Known issues / feature gaps - C6 state is not supported. Workaround is to disable C6 support through - target OS and Linuxboot kernel paramter, such as "cpuidle.off=1". + target OS and Linuxboot kernel parameter, such as "cpuidle.off=1". - SMI handlers are not implemented. - xSDT tables are not fully populated, such as processor/socket devices, PCIe bridge devices. diff --git a/Documentation/mainboard/up/squared/index.md b/Documentation/mainboard/up/squared/index.md index d07f111..2895e1f 100644 --- a/Documentation/mainboard/up/squared/index.md +++ b/Documentation/mainboard/up/squared/index.md @@ -48,7 +48,7 @@ +---------------------+------------+ | Internal flashing | No | +---------------------+------------+ -| In curcuit flashing | Yes | +| In circuit flashing | Yes | +---------------------+------------+ ``` @@ -67,8 +67,8 @@ The SPI header is located on the **bottom** side (see [here][overview_bottom_link]). ![][header_cn22] -### Preperations -In order to build coreboot, it's neccessary to extract some files from the vendor firmware. Make sure that you have a fully working dump. +### Preparations +In order to build coreboot, it's necessary to extract some files from the vendor firmware. Make sure that you have a fully working dump. ```bash [upsquared]$ ls firmware_vendor.rom diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index bf0b89f..1cd5fb4 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -40,7 +40,7 @@ +---------+-------------------------------------------------------------------+------------+--------------+ ``` -## (Unoffical) register documentation +## (Unofficial) register documentation - [Sandy Bridge - Register documentation](nri_registers.md) ## Frequency selection @@ -101,7 +101,7 @@ As of writing the only supported error handling is to disable the failing channel and restart the memory training sequence. It's very likely to succeed, as memory channels operate independent of each other. -In case no DIMM could be initilized coreboot will halt. The screen will stay +In case no DIMM could be initialized coreboot will halt. The screen will stay black until you power of your device. On some platforms there's additional feedback to indicate such an event. diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index 208c1cb..8d66b5c 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -42,7 +42,7 @@ * 1.5V operating voltage * The channel's installed DIMM count doesn't exceed the XMP coded limit -In case the XMP profile doesn't fullfill those limits, the regular SPD will be +In case the XMP profile doesn't fulfill those limits, the regular SPD will be used. > **Note:** XMP Profiles are supported since coreboot 4.4. diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index aae1205..32bd3d1 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1947,7 +1947,7 @@ +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ -| 0:7| OREF_RI, Rank idle period that defines an oppertunity for | +| 0:7| OREF_RI, Rank idle period that defines an opportunity for | | | refresh | +-----------+------------------------------------------------------------------+ | 8:11| Refresh_HP_WM, tREFI count level that turns the refresh | diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 971d438..600bf67 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -200,7 +200,7 @@ ### Resource allocator v4 A new revision of resource allocator v4 is now added to coreboot that supports -mutiple ranges for allocating resources. Unlike the previous allocator (v3), it does +multiple ranges for allocating resources. Unlike the previous allocator (v3), it does not use the topmost available window for allocation. Instead, it uses the first window within the address space that is available and satisfies the resource request. This allows utilization of the entire available address space and also allows diff --git a/Documentation/releases/coreboot-4.3-relnotes.md b/Documentation/releases/coreboot-4.3-relnotes.md index c33c48a..c0dda6e 100644 --- a/Documentation/releases/coreboot-4.3-relnotes.md +++ b/Documentation/releases/coreboot-4.3-relnotes.md @@ -124,7 +124,7 @@ Areas with significant work on updates and fixes ------------------------------------------------ * cpu/amd/model_fxx -* intel/fsp1_x: Fix timestanps & postcodes, add native CAR & microcode +* intel/fsp1_x: Fix timestamps & postcodes, add native CAR & microcode * nb/amd/amdfam10: Add S3, voltage & ACPI, speed fixes & MANY other changes * nb/amd/amdmct: Add S3, mem voltage, Fix performance & MANY other diff --git a/Documentation/security/intel/txt.md b/Documentation/security/intel/txt.md index f80a731..7a746ec 100644 --- a/Documentation/security/intel/txt.md +++ b/Documentation/security/intel/txt.md @@ -37,7 +37,7 @@ ### Measurements The IBBs (Initial Boot Blocks) are measured into TPM's PCR0 by the BIOS [ACM] -before the CPU reset vector is executed. To indentify the regions that need +before the CPU reset vector is executed. To identify the regions that need to be measured, the [FIT] contains one ore multiple *Type 7* entries, that point to the IBBs. diff --git a/Documentation/security/smm.md b/Documentation/security/smm.md index 4e95427..397b7af 100644 --- a/Documentation/security/smm.md +++ b/Documentation/security/smm.md @@ -1,4 +1,4 @@ -# x86 System Managment Mode +# x86 System Management Mode ## Introduction @@ -6,7 +6,7 @@ to applications running in [ring0]. It has a higher privilege level than [ring0] and resides in the SMRAM region which cannot be accessed from [ring0]. -SMM can be entered by issuing System Managment Interrupts (SMIs). +SMM can be entered by issuing System Management Interrupts (SMIs). ## Secure data exchange diff --git a/Documentation/security/vboot/measured_boot.md b/Documentation/security/vboot/measured_boot.md index df4cc68..adfae46 100644 --- a/Documentation/security/vboot/measured_boot.md +++ b/Documentation/security/vboot/measured_boot.md @@ -9,7 +9,7 @@ code block loaded at reset vector and measured by a DRTM solution. In case SRTM mode is active, the IBB measures itself before measuring the next code block. In coreboot, cbfs files which are part of the IBB are identified -by a metatdata tag. This makes it possible to have platform specific IBB +by a metadata tag. This makes it possible to have platform specific IBB measurements without hardcoding them. ## Known Limitations diff --git a/Documentation/soc/cavium/cn81xx/index.md b/Documentation/soc/cavium/cn81xx/index.md index 3063b94..684948c 100644 --- a/Documentation/soc/cavium/cn81xx/index.md +++ b/Documentation/soc/cavium/cn81xx/index.md @@ -21,7 +21,7 @@ * Secondary CPUs * PCI -All other hardware is initilized by the BDK code, which is invoked from +All other hardware is initialized by the BDK code, which is invoked from ramstage. ## Notes about the hardware diff --git a/Documentation/superio/common/ssdt.md b/Documentation/superio/common/ssdt.md index 2f4049e..5f9e2f6 100644 --- a/Documentation/superio/common/ssdt.md +++ b/Documentation/superio/common/ssdt.md @@ -50,7 +50,7 @@ The following methods are generated for each SuperIO: ## AMTX() Acquire the global mutex and enter config mode. -It's called this at the begining of an atomic operation to make sure +It's called this at the beginning of an atomic operation to make sure no other ACPI code messes with the config space while working on it. ## RMTX() @@ -63,7 +63,7 @@ ## DLDN(Arg0) Disables the (virtual) LDN given as Arg0. -This method aquires the global mutex. +This method acquires the global mutex. ## QLDN(Arg0) Queries the state of the (virtual) LDN given as Arg0. diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md index f7fe1a5..11a0a88 100644 --- a/Documentation/superio/nuvoton/npcd378.md +++ b/Documentation/superio/nuvoton/npcd378.md @@ -4,7 +4,7 @@ mainboards. As no datasheet is available most of the functions have been reverse engineered and -might be inacurate or wrong. +might be inaccurate or wrong. ## LDNs diff --git a/Documentation/technotes/2020-03-unit-testing-coreboot.md b/Documentation/technotes/2020-03-unit-testing-coreboot.md index 02c2e30..a4d283f 100644 --- a/Documentation/technotes/2020-03-unit-testing-coreboot.md +++ b/Documentation/technotes/2020-03-unit-testing-coreboot.md @@ -83,7 +83,7 @@ Compiler for the host _must_ support the same language standards as the target compiler. Ideally the same toolchain should be used for building firmware - executables and test binaries, however the host complier will be used to build + executables and test binaries, however the host compiler will be used to build unit tests, whereas the coreboot toolchain will be used for building the firmware executables. For some targets, the host compiler and the target compiler could be the same, but this is not a requirement. diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index e02812b..8702488 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -123,7 +123,7 @@ of the same version. If you started with a different distribution or package management system you -might need to install other packages. Most likely they are named sightly +might need to install other packages. Most likely they are named slightly different. If that is the case for you, we'd like to encourage you to contribute to the project and submit a pull request with an update for this documentation for your system. diff --git a/Documentation/util.md b/Documentation/util.md index 083401f..8c6bcb7 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -57,7 +57,7 @@ hardware configuration (register contents, MSRs, etc). `C` * __intelvbttool__ - Parse VBT from VGA BIOS `C` * __ipqheader__ - * _createxbl.py_ - Concatentates XBL segments into one ELF + * _createxbl.py_ - Concatenates XBL segments into one ELF image `Python` * _ipqheader.py_ - Returns a packed MBN header image with the specified base and size `Python` -- To view, visit https://review.coreboot.org/c/coreboot/+/58078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8 Gerrit-Change-Number: 58078 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation/RFC: Generalize PCI support in coreboot
by Shelley Chen (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Shelley Chen, Felix Singer, Nico Huber, Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Paul Menzel, Julius Werner, Angel Pons, Kyösti Mälkki. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Paul Menzel, Julius Werner, Angel Pons, Kyösti Mälkki, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57861 to look at the new patch set (#9). Change subject: Documentation/RFC: Generalize PCI support in coreboot ...................................................................... Documentation/RFC: Generalize PCI support in coreboot Design Doc describing how we would refactor the mmio accesses in the PCI config space in coreboot so that we can extend the support to platforms that do not support ECAM. BUG=b:181098581 BRANCH=None TEST=None Change-Id: I3a56d932f6e047087c38a7687564065cc1562363 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A Documentation/RFC/pci_config_access.md A Documentation/RFC/sys_mem_map.jpg 2 files changed, 119 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/57861/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/57861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a56d932f6e047087c38a7687564065cc1562363 Gerrit-Change-Number: 57861 Gerrit-PatchSet: 9 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Helper function to check CSE device `devfn` status
by Subrata Banik (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58064 ) Change subject: soc/intel/common: Helper function to check CSE device `devfn` status ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/58064/comment/83fa560c_2010a589 PS4, Line 156: ` > Ack @Tim, can you please share your vote ? -- To view, visit https://review.coreboot.org/c/coreboot/+/58064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0 Gerrit-Change-Number: 58064 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 05 Oct 2021 17:21:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2021