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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57888 )
Change subject: soc/amd/cezanne,soc/intel/common: rework CPPC table generation
......................................................................
Patch Set 12:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/f35fd8b9_0347af49
PS12, Line 108: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/39def05a_09a46c4b
PS12, Line 110: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/d6854536_8027bee8
PS12, Line 111: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/1a503513_86f10c89
PS12, Line 112: config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/bd213a4b_5e3c57c4
PS12, Line 135: config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10);
line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/bec1ddde_10dfb3ca
PS12, Line 18: config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/f035eadb_fb18a92d
PS12, Line 19: config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/8a7bb805_1ce645b3
PS12, Line 20: config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/31ed55cc_055f4d3b
PS12, Line 21: config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/593c7e74_a1d87962
PS12, Line 23: config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/5b6293df_f8485d76
PS12, Line 24: config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/a309b9ad_6370cfad
PS12, Line 25: config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/1240fa15_ad87787c
PS12, Line 29: config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/1127debd_0b5aa7ac
PS12, Line 30: config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129825):
https://review.coreboot.org/c/coreboot/+/57888/comment/23c5ec9c_af8b5262
PS12, Line 39: config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
line over 96 characters
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Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Marshall Dawson, Tim Wawrzynczak, Felix Held.
Hello Felix Singer, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Tim Wawrzynczak, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57888
to look at the new patch set (#12).
Change subject: soc/amd/cezanne,soc/intel/common: rework CPPC table generation
......................................................................
soc/amd/cezanne,soc/intel/common: rework CPPC table generation
Make use of the newly introduced ACPI macros for CPPC table generation
that currently exists of a bunch of confusing assignments of structs
that only get filled partly.
Change-Id: I844d191b1134b98e409240ede71e2751e51e2159
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpi.h
M src/soc/amd/cezanne/cppc.c
3 files changed, 58 insertions(+), 317 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/57888/12
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Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held.
Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Lance Zhao, Matt Delco, Nico Huber, Tim Wawrzynczak, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
Some elements in the ACPI CPPC table allow static DWORDs. Instead of
using a fake register resource, use a tagged union with the two types
"register" and "DWORD" and respective macros for CPPC table entries.
Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/acpi/acpigen.h
M src/soc/amd/cezanne/cppc.c
M src/soc/amd/cezanne/include/soc/cppc.h
6 files changed, 69 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/57886/5
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58099 )
Change subject: mb/adlrvp: Add hook function to return EC in RW status
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/intel/adlrvp/chromeos.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129822):
https://review.coreboot.org/c/coreboot/+/58099/comment/01b26b26_a2792e2d
PS5, Line 56: #endif
adding a line without newline at end of file
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Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58099 )
Change subject: mb/adlrvp: Add hook function to return EC in RW status
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/intel/adlrvp/chromeos.c:
https://review.coreboot.org/c/coreboot/+/58099/comment/e70c8654_60539525
PS4, Line 50: int get_ec_is_trusted(void)
: {
: /* EC is trusted if not in RW. */
: return !gpio_get(GPIO_EC_IN_RW);
: }
> There is nothing left in depthcharge to handle that "EC in RW" gpios. […]
got it. will do.
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58115 )
Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/psp/psp_efs.c:
https://review.coreboot.org/c/coreboot/+/58115/comment/d15719c4_27916827
PS1, Line 14: efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs));
What is the reasoning for changing this?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57140 )
Change subject: soc/tigerlake: Make IO decode / enable register configurable
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
> Do you mean […]
Yep. The only difference for newer platforms is that there are these DMI
registers that need the values mirrored. I don't see the need for the
complex soc/intel/common/ code, neither for anything platform specific.
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Gerrit-Change-Number: 57140
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Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com>
Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com>
Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-CC: Nico Huber <nico.h(a)gmx.de>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Comment-Date: Tue, 05 Oct 2021 20:54:23 +0000
Gerrit-HasComments: Yes
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Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>
Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-MessageType: comment