coreboot-gerrit October 2021

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Change in coreboot[master]: mb/google/brya/var/brask: Enable RTL8125
by build bot (Jenkins) (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58105 ) Change subject: mb/google/brya/var/brask: Enable RTL8125 ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/Kconfig: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129794): https://review.coreboot.org/c/coreboot/+/58105/comment/3d1c8c16_201cbab3 PS1, Line 11: select RT8168_SET_LED_MODE trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Oct 2021 07:52:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: Enable RTL8125
by Alan Huang (Code Review) 05 Oct '21

05 Oct '21

Alan Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58105 ) Change subject: mb/google/brya/var/brask: Enable RTL8125 ...................................................................... mb/google/brya/var/brask: Enable RTL8125 Update the GPIOs and parameters of RTL8125 in the devicetree. Add config RT8168_GET_MAC_FROM_VPD and RT8168_SET_LED_MODE for brask to apply the RT8168 driver (r8168.c) which contains functions to read MAC address and customize the LED settings. BUG=b:193750191 BRANCH=None TEST=build pass Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/58105/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e6e44e2..69bad5c 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -7,6 +7,8 @@ config BOARD_GOOGLE_BASEBOARD_BRASK def_bool n select SPD_CACHE_IN_FMAP + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index e707a9b..dfcc102 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -1,6 +1,18 @@ chip soc/intel/alderlake device domain 0 on + device ref pcie_rp7 on + chip drivers/net + register "customized_leds" = "0x05af" + # register "wake" = "GPE0_DW1_07" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # RTL8125 Ethernet NIC end end -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add PsysPmax setting to 145W
by Ryan Lin (Code Review) 05 Oct '21

05 Oct '21

Ryan Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58104 ) Change subject: mb/google/brya: Add PsysPmax setting to 145W ...................................................................... mb/google/brya: Add PsysPmax setting to 145W This patch adds the setting of PsysPmax to 145W according to the brya board design. BUG=b:195615830 TEST=emerge-brya coreboot chromeos-bootimage & Ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Signed-off-by: Ryan Lin <ryan.lin(a)intel.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/58104/1 diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 41d1018..ad2399b 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -32,6 +32,8 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" + register "PsysPmax" = "145" + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port -- To view, visit https://review.coreboot.org/c/coreboot/+/58104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Gerrit-Change-Number: 58104 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Lin <ryan.lin(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC,WIP] cpu/x86/lapic: Drop xapic_write_atomic()
by ron minnich (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Kyösti Mälkki. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55199 ) Change subject: [RFC,WIP] cpu/x86/lapic: Drop xapic_write_atomic() ...................................................................... Patch Set 12: Code-Review+1 (1 comment) Patchset: PS12: Very nice! Is it safe to say that every single x86 in our tree supports x2apic? I am wondering if we could use that as the criteria. Or is it sufficient to say that the 0x520 is gone, and as a result, we can just take this. -- To view, visit https://review.coreboot.org/c/coreboot/+/55199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec10335f603674bcef2e7494831cf11200795d38 Gerrit-Change-Number: 55199 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 06:37:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Fix SMBIOS type 9 bugs
by Johnny Lin (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jonathan Zhang, Christian Walter, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang, Tim Chu, Shelly_Chang(a)wiwynn.com. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58100 ) Change subject: mb/ocp/deltalake: Fix SMBIOS type 9 bugs ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9 Gerrit-Change-Number: 58100 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shelly_Chang(a)wiwynn.com Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Shelly_Chang(a)wiwynn.com Gerrit-Comment-Date: Tue, 05 Oct 2021 06:11:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Fix SMBIOS type 9 bugs
by Johnny Lin (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jonathan Zhang, Christian Walter, Jingle Hsu, Arthur Heymans, Tim Chu, Shelly_Chang(a)wiwynn.com. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58100 ) Change subject: mb/ocp/deltalake: Fix SMBIOS type 9 bugs ...................................................................... Patch Set 3: (1 comment) This change is ready for review. File src/mainboard/ocp/deltalake/ramstage.c: https://review.coreboot.org/c/coreboot/+/58100/comment/4dea0d42_7881a136 PS3, Line 281: be aligned with our UEFI reference BIOS. */ > This is a bug in UEFI, isn't it? Does FB depend on the incorrect implementation of UEFI? If this is […] True but at least for Delta Lake FB doesn't depend on the BDF numbers in SMBIOS type 9 and we will make it compatible with the spec in the future projects. -- To view, visit https://review.coreboot.org/c/coreboot/+/58100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9 Gerrit-Change-Number: 58100 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Shelly_Chang(a)wiwynn.com Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Shelly_Chang(a)wiwynn.com Gerrit-Comment-Date: Tue, 05 Oct 2021 06:04:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 05 Oct '21

05 Oct '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57345 ) Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... driver/intel/pmc_mux/conn: Add type-c port info to cbmem This change adds type-c port information for USB type-c ports to cbmem. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57345 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/intel/pmc_mux/conn/conn.c 1 file changed, 64 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index 7a622c8..caff166 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -2,11 +2,73 @@ #include <acpi/acpigen.h> #include <boot/coreboot_tables.h> +#include <cbmem.h> #include <console/console.h> #include <intelblocks/acpi.h> #include "chip.h" +/* Number of registered connectors */ +static size_t total_conn_count; + +static void conn_init(struct device *dev) +{ + total_conn_count++; +} + +static struct type_c_info *conn_get_cbmem_buffer(void) +{ + struct type_c_info *info; + size_t size; + + info = cbmem_find(CBMEM_ID_TYPE_C_INFO); + if (info) + return info; + + size = sizeof(struct type_c_info) + total_conn_count * sizeof(struct type_c_port_info); + info = cbmem_add(CBMEM_ID_TYPE_C_INFO, size); + + if (!info) + return NULL; + + memset(info, 0, size); + return info; +} + +static void conn_write_cbmem_entry(struct device *dev) +{ + const struct drivers_intel_pmc_mux_conn_config *config = dev->chip_info; + struct type_c_port_info *port_info; + struct type_c_info *info; + size_t count; + + /* + * Do not re-run this code on resume as the cbmem data is populated on boot-up + * (non-S3 path) and stays intact across S3 suspend/resume. + */ + if (acpi_is_wakeup_s3()) + return; + + info = conn_get_cbmem_buffer(); + if (!info || (info->port_count >= total_conn_count)) { + printk(BIOS_ERR, "ERROR: No space for Type-C port info!\n"); + return; + } + + count = info->port_count; + port_info = &info->port_info[count]; + port_info->usb2_port_number = config->usb2_port_number; + port_info->usb3_port_number = config->usb3_port_number; + port_info->sbu_orientation = config->sbu_orientation; + port_info->data_orientation = config->hsl_orientation; + + printk(BIOS_INFO, "added type-c port%ld info to cbmem: usb2:%d usb3:%d sbu:%d data:%d\n", + count, port_info->usb2_port_number, port_info->usb3_port_number, + port_info->sbu_orientation, port_info->data_orientation); + + info->port_count++; +} + static const char *conn_acpi_name(const struct device *dev) { static char name[5]; @@ -76,6 +138,8 @@ .set_resources = noop_set_resources, .acpi_name = conn_acpi_name, .acpi_fill_ssdt = conn_fill_ssdt, + .init = conn_init, + .final = conn_write_cbmem_entry, }; static void conn_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 24 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support
by Ian Feng (Code Review) 05 Oct '21

05 Oct '21

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58102 ) Change subject: mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support ...................................................................... mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support Add ALC5682-VS codec support in corori. ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO field of ssfc. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:201372531, b:194436265 TEST=ALC5682-VD/ALC5682-VS audio codec can work. Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I2f3edb0b594066714b42050a411103a215e68b12 --- M src/mainboard/google/dedede/variants/corori/overridetree.cb 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/58102/1 diff --git a/src/mainboard/google/dedede/variants/corori/overridetree.cb b/src/mainboard/google/dedede/variants/corori/overridetree.cb index 33c0542..d322000 100644 --- a/src/mainboard/google/dedede/variants/corori/overridetree.cb +++ b/src/mainboard/google/dedede/variants/corori/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end + chip soc/intel/jasperlake # USB Port Configuration @@ -124,7 +132,24 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end end end #I2C 4 device pci 1e.2 off end # GSPI 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/58102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f3edb0b594066714b42050a411103a215e68b12 Gerrit-Change-Number: 58102 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/adlrvp: Add hook function to return EC in RW status
by Hsuan-ting Chen (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Bernardo Perez Priego. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58099 ) Change subject: mb/adlrvp: Add hook function to return EC in RW status ...................................................................... Patch Set 4: (1 comment) File src/mainboard/intel/adlrvp/chromeos.c: https://review.coreboot.org/c/coreboot/+/58099/comment/93358ca3_bad55eda PS4, Line 50: int get_ec_is_trusted(void) : { : /* EC is trusted if not in RW. */ : return !gpio_get(GPIO_EC_IN_RW); : } There is nothing left in depthcharge to handle that "EC in RW" gpios. (removed at: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/…) Now, the equivalent logic is moved to coreboot and handled by this function. So I think we should guard this function as well. (It will use the default __weak function in src/third_party/coreboot/src/security/vboot/bootmode.c instead, which always returns false) -- To view, visit https://review.coreboot.org/c/coreboot/+/58099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Gerrit-Change-Number: 58099 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 02:18:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Hook up GMA ACPI brightness controls
by Tim Crawford (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Tim Crawford, Tim Wawrzynczak, Michael Niewöhner. Hello build bot (Jenkins), Matt DeVillier, Tim Wawrzynczak, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57823 to look at the new patch set (#3). Change subject: soc/intel/tigerlake: Hook up GMA ACPI brightness controls ...................................................................... soc/intel/tigerlake: Hook up GMA ACPI brightness controls Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/gaze16 and booting Windows. Display settings has a brightness setting, and can change the brightness level. Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/graphics.c 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/57823/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/57823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373 Gerrit-Change-Number: 57823 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2021