coreboot-gerrit October 2021

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Change in coreboot[master]: mb/adlrvp: Add hook function to return EC in RW status
by Hsuan-ting Chen (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Bernardo Perez Priego. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58099 ) Change subject: mb/adlrvp: Add hook function to return EC in RW status ...................................................................... Patch Set 4: (1 comment) File src/mainboard/intel/adlrvp/chromeos.c: https://review.coreboot.org/c/coreboot/+/58099/comment/93358ca3_bad55eda PS4, Line 50: int get_ec_is_trusted(void) : { : /* EC is trusted if not in RW. */ : return !gpio_get(GPIO_EC_IN_RW); : } There is nothing left in depthcharge to handle that "EC in RW" gpios. (removed at: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/…) Now, the equivalent logic is moved to coreboot and handled by this function. So I think we should guard this function as well. (It will use the default __weak function in src/third_party/coreboot/src/security/vboot/bootmode.c instead, which always returns false) -- To view, visit https://review.coreboot.org/c/coreboot/+/58099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Gerrit-Change-Number: 58099 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 02:18:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Hook up GMA ACPI brightness controls
by Tim Crawford (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Tim Crawford, Tim Wawrzynczak, Michael Niewöhner. Hello build bot (Jenkins), Matt DeVillier, Tim Wawrzynczak, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57823 to look at the new patch set (#3). Change subject: soc/intel/tigerlake: Hook up GMA ACPI brightness controls ...................................................................... soc/intel/tigerlake: Hook up GMA ACPI brightness controls Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/gaze16 and booting Windows. Display settings has a brightness setting, and can change the brightness level. Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/graphics.c 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/57823/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/57823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373 Gerrit-Change-Number: 57823 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Hello build bot (Jenkins), Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58101 to look at the new patch set (#5). Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 with this change, we won't get this warning message: 'Defaulting to using DDR4 params. Please add dram_type check for 19 to use_ddr4_params' Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M src/lib/spd_bin.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Hello build bot (Jenkins), Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58101 to look at the new patch set (#4). Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 with this change, we won't get: fix coreboot warning: 'Defaulting to using DDR4 params. Please add dram_type check for 19 to use_ddr4_params' Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M src/lib/spd_bin.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Hello build bot (Jenkins), Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58101 to look at the new patch set (#3). Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M src/lib/spd_bin.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Hello build bot (Jenkins), Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58101 to look at the new patch set (#2). Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M 3rdparty/blobs M 3rdparty/fsp M src/lib/spd_bin.c 3 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Selma Bensaid (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58101 ) Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58101/comment/158a29d5_e6a8575e PS1, Line 9: Added LDDR5 for the param : Fixed SPD name for LDDR5 Please remove the space -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 01:12:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add mock architecture
by Julius Werner (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jakub Czapiga, Paul Menzel, Jan Dabros. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57708 ) Change subject: libpayload: Add mock architecture ...................................................................... Patch Set 8: (6 comments) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/57708/comment/dcc369ae_42bb375e PS7, Line 480: default y > Done. However I have no idea, how to make BIG_ENDIAN=y possible. […] That's because this doesn't have prompt string (after the `bool`) so it's not a "visible"/user-changeable option for Kconfig. It's not supposed to be either because usually this is a hard dependency on the architecture that cannot change, but the mock architecture is a special case, so you can model this with an extra ARCH_MOCK_BIG_ENDIAN option in arch/mock/Kconfig that does have a prompt string (and will then cause it to `select` the right option here). File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/57708/comment/40ad35b3_6f77055f PS8, Line 125: MOCK This could look a bit nicer (e.g. "Mock architecture (for unit tests)"). File payloads/libpayload/Makefile: https://review.coreboot.org/c/coreboot/+/57708/comment/4b7de264_fa6231df PS8, Line 162: host mock https://review.coreboot.org/c/coreboot/+/57708/comment/b7daccd8_9d989631 PS8, Line 164: host ditto File payloads/libpayload/arch/mock/head.c: https://review.coreboot.org/c/coreboot/+/57708/comment/77d7139a_9ddfc247 PS8, Line 3: /* This file is empty on purpose. It should not be used. */ Then why does it exist? I still don't get it. Just take it out of the Makefile? File payloads/libpayload/include/mock/arch/io.h: https://review.coreboot.org/c/coreboot/+/57708/comment/d31a9ed7_faef6d2b PS8, Line 7: Maybe explain that tests are expected to implement mocks for these if they want to test code that calls them. -- To view, visit https://review.coreboot.org/c/coreboot/+/57708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Gerrit-Change-Number: 57708 Gerrit-PatchSet: 8 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 01:11:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58101 ) Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M 3rdparty/blobs M 3rdparty/fsp M src/lib/spd_bin.c 3 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index f388b67..8c4e2c8 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit f388b6794e6f1f93b847de353f5eab8ba3e3b328 +Subproject commit 8c4e2c83362c48154d954aa657b805e0681977b0 diff --git a/3rdparty/fsp b/3rdparty/fsp index 10eae55..cc17338 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 10eae55b8eb0febfa2dfabf4017701b072866170 +Subproject commit cc173384ec4152cde81020da88a2f6cf9c6edfac diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 865f16c..9c8681e 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -34,6 +34,7 @@ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: return true; @@ -165,6 +166,7 @@ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: *spd_name = (const char *) &spd[DDR4_SPD_PART_OFF]; -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/vboot: Remove vb2ex_hwcrypto stubs
by Julius Werner (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58095 ) Change subject: security/vboot: Remove vb2ex_hwcrypto stubs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62bdc647eb3e34c581cc1b8d15e7f271211e6156 Gerrit-Change-Number: 58095 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 00:49:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2021