coreboot-gerrit October 2021

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Hello build bot (Jenkins), Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58101 to look at the new patch set (#5). Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 with this change, we won't get this warning message: 'Defaulting to using DDR4 params. Please add dram_type check for 19 to use_ddr4_params' Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M src/lib/spd_bin.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Hello build bot (Jenkins), Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58101 to look at the new patch set (#4). Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 with this change, we won't get: fix coreboot warning: 'Defaulting to using DDR4 params. Please add dram_type check for 19 to use_ddr4_params' Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M src/lib/spd_bin.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Hello build bot (Jenkins), Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58101 to look at the new patch set (#3). Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M src/lib/spd_bin.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Hello build bot (Jenkins), Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58101 to look at the new patch set (#2). Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M 3rdparty/blobs M 3rdparty/fsp M src/lib/spd_bin.c 3 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Selma Bensaid (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Cliff Huang. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58101 ) Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58101/comment/158a29d5_e6a8575e PS1, Line 9: Added LDDR5 for the param : Fixed SPD name for LDDR5 Please remove the space -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 01:12:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add mock architecture
by Julius Werner (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Jakub Czapiga, Paul Menzel, Jan Dabros. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57708 ) Change subject: libpayload: Add mock architecture ...................................................................... Patch Set 8: (6 comments) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/57708/comment/dcc369ae_42bb375e PS7, Line 480: default y > Done. However I have no idea, how to make BIG_ENDIAN=y possible. […] That's because this doesn't have prompt string (after the `bool`) so it's not a "visible"/user-changeable option for Kconfig. It's not supposed to be either because usually this is a hard dependency on the architecture that cannot change, but the mock architecture is a special case, so you can model this with an extra ARCH_MOCK_BIG_ENDIAN option in arch/mock/Kconfig that does have a prompt string (and will then cause it to `select` the right option here). File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/57708/comment/40ad35b3_6f77055f PS8, Line 125: MOCK This could look a bit nicer (e.g. "Mock architecture (for unit tests)"). File payloads/libpayload/Makefile: https://review.coreboot.org/c/coreboot/+/57708/comment/4b7de264_fa6231df PS8, Line 162: host mock https://review.coreboot.org/c/coreboot/+/57708/comment/b7daccd8_9d989631 PS8, Line 164: host ditto File payloads/libpayload/arch/mock/head.c: https://review.coreboot.org/c/coreboot/+/57708/comment/77d7139a_9ddfc247 PS8, Line 3: /* This file is empty on purpose. It should not be used. */ Then why does it exist? I still don't get it. Just take it out of the Makefile? File payloads/libpayload/include/mock/arch/io.h: https://review.coreboot.org/c/coreboot/+/57708/comment/d31a9ed7_faef6d2b PS8, Line 7: Maybe explain that tests are expected to implement mocks for these if they want to test code that calls them. -- To view, visit https://review.coreboot.org/c/coreboot/+/57708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Gerrit-Change-Number: 57708 Gerrit-PatchSet: 8 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 01:11:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 05 Oct '21

05 Oct '21

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58101 ) Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 Added LDDR5 for the param Fixed SPD name for LDDR5 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M 3rdparty/blobs M 3rdparty/fsp M src/lib/spd_bin.c 3 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index f388b67..8c4e2c8 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit f388b6794e6f1f93b847de353f5eab8ba3e3b328 +Subproject commit 8c4e2c83362c48154d954aa657b805e0681977b0 diff --git a/3rdparty/fsp b/3rdparty/fsp index 10eae55..cc17338 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 10eae55b8eb0febfa2dfabf4017701b072866170 +Subproject commit cc173384ec4152cde81020da88a2f6cf9c6edfac diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 865f16c..9c8681e 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -34,6 +34,7 @@ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: return true; @@ -165,6 +166,7 @@ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: *spd_name = (const char *) &spd[DDR4_SPD_PART_OFF]; -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/vboot: Remove vb2ex_hwcrypto stubs
by Julius Werner (Code Review) 05 Oct '21

05 Oct '21

Attention is currently required from: Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58095 ) Change subject: security/vboot: Remove vb2ex_hwcrypto stubs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62bdc647eb3e34c581cc1b8d15e7f271211e6156 Gerrit-Change-Number: 58095 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 05 Oct 2021 00:49:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Fix SMBIOS type 9 bugs
by Johnny Lin (Code Review) 05 Oct '21

05 Oct '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58100 ) Change subject: mb/ocp/deltalake: Fix SMBIOS type 9 bugs ...................................................................... mb/ocp/deltalake: Fix SMBIOS type 9 bugs 1. Fix PCIe slot capabilities was not really read from an IIO root port device. The Hot-Plug capability of IIO root port cannot be enabled due to FSP limitation, but the code should reflect the true capabilities by reading the root port device's CSR. 2. Clear the flag before the next for-loop iteration. Tested=On OCP Delta Lake, dmidecode -t 9 shows expected results. Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 12 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/58100/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 8d9de82..cdcfe83 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -198,7 +198,7 @@ uint8_t characteristics_2 = 0; uint32_t vendor_device_id; uint8_t stack_busnos[MAX_IIO_STACK]; - pci_devfn_t pci_dev; + pci_devfn_t pci_dev_slot, pci_dev = 0; unsigned int cap; uint16_t sltcap; @@ -251,14 +251,14 @@ else slot_length = SlotLengthShort; - pci_dev = PCI_DEV(stack_busnos[slotinfo[index].stack], + pci_dev_slot = PCI_DEV(stack_busnos[slotinfo[index].stack], slotinfo[index].dev_func >> 3, slotinfo[index].dev_func & 0x7); - sec_bus = pci_s_read_config8(pci_dev, PCI_SECONDARY_BUS); + sec_bus = pci_s_read_config8(pci_dev_slot, PCI_SECONDARY_BUS); if (sec_bus == 0xFF) { slot_usage = SlotUsageUnknown; } else { - /* Checking for Slot device availability */ + /* Checking for downstream device availability */ pci_dev = PCI_DEV(sec_bus, 0, 0); vendor_device_id = pci_s_read_config32(pci_dev, 0); if (vendor_device_id == 0xFFFFFFFF) @@ -269,13 +269,16 @@ characteristics_1 |= SMBIOS_SLOT_3P3V; // Provides33Volts characteristics_2 |= SMBIOS_SLOT_PME; // PmeSiganalSupported - - cap = pci_s_find_capability(pci_dev, PCI_CAP_ID_PCIE); - sltcap = pci_s_read_config16(pci_dev, cap + PCI_EXP_SLTCAP); + /* Read IIO root port device CSR for slot capabilities */ + cap = pci_s_find_capability(pci_dev_slot, PCI_CAP_ID_PCIE); + sltcap = pci_s_read_config16(pci_dev_slot, cap + PCI_EXP_SLTCAP); if (sltcap & PCI_EXP_SLTCAP_HPC) characteristics_2 |= SMBIOS_SLOT_HOTPLUG; const uint16_t slot_id = index + 1; + /* According to SMBIOS spec, the BDF number should be the end + point on the slot, for now we keep using the root port's BDF to + be aligned with our UEFI reference BIOS. */ length += smbios_write_type9(current, handle, slotinfo[index].slot_designator, slotinfo[index].slot_type, @@ -287,6 +290,8 @@ characteristics_2, stack_busnos[slotinfo[index].stack], slotinfo[index].dev_func); + characteristics_1 = 0; + characteristics_2 = 0; } return length; -- To view, visit https://review.coreboot.org/c/coreboot/+/58100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9 Gerrit-Change-Number: 58100 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Implement __weak smihandler_soc_disable_busmaster
by Kane Chen (Code Review) 05 Oct '21

05 Oct '21

Kane Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58093 ) Change subject: soc/intel/common: Implement __weak smihandler_soc_disable_busmaster ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/58093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ed7e6a3f60588bfb90481ea493495080dbbfd58 Gerrit-Change-Number: 58093 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit October 2021