coreboot-gerrit October 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/tigerlake: Make IO decode / enable register configurable
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57140 ) Change subject: soc/tigerlake: Make IO decode / enable register configurable ...................................................................... Patch Set 19: (1 comment) Patchset: PS19: > `src/southbridge/intel/bd82x6x/early_pch.c` is probably not a bad […] Do you mean ``` pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); ``` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/57140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3 Gerrit-Change-Number: 57140 Gerrit-PatchSet: 19 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 20:39:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Furquan Shaikh (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57345 ) Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... Patch Set 22: Code-Review+2 (1 comment) File src/drivers/intel/pmc_mux/conn/conn.c: https://review.coreboot.org/c/coreboot/+/57345/comment/fd68ae29_a1ff2d76 PS22, Line 45: */ Can you please add the *why* as well? i.e. the cbmem data is populated on boot-up (non-S3 path) and stays intact across S3 suspend/resume. -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 22 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 20:35:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57345 ) Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... Patch Set 22: (2 comments) File src/drivers/intel/pmc_mux/conn/conn.c: https://review.coreboot.org/c/coreboot/+/57345/comment/6e07a16e_044f2cc0 PS20, Line 47: if (!acpi_is_wakeup_s3()) > This check should be the first thing in the function so that you don't need to get cbmem buffer, etc […] Done https://review.coreboot.org/c/coreboot/+/57345/comment/b97b4751_74d3ca94 PS20, Line 47: if (!acpi_is_wakeup_s3()) > nit: this looks like it will work, I just think it makes more sense as a separate check, i.e. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 22 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 20:30:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Nico Huber, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57345 to look at the new patch set (#22). Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... driver/intel/pmc_mux/conn: Add type-c port info to cbmem This change adds type-c port information for USB type-c ports to cbmem. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/drivers/intel/pmc_mux/conn/conn.c 1 file changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/57345/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 22 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Nico Huber, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57345 to look at the new patch set (#21). Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... driver/intel/pmc_mux/conn: Add type-c port info to cbmem This change adds type-c port information for USB type-c ports to cbmem. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/drivers/intel/pmc_mux/conn/conn.c 1 file changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/57345/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 21 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: deduplicate acpi_fill_soc_wake
by Michael Niewöhner (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Duncan Laurie, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58043 ) Change subject: soc/intel: deduplicate acpi_fill_soc_wake ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/58043/comment/10906cc3_48617993 PS1, Line 220: RTC_EN > I guess, if this power-well oddity exists at all, the correct way to deal > with it would be to capture the EN state when suspending. (An actual > use-case for GNVS?) We already save some stuff in cbmem, see `pmc_get_power_state` and `migrate_power_state` in `src/soc/intel/common/block/pmc/pmclib.c`. Maybe we can use that for PM1_EN too, and hook it in S3? > I already tested this for the Deep Sx registers. They are, as the datasheet says, in the RTC powerwell. > > I will test LAN_WAKE_EN, RTC_EN later Tested: DSX_CFG and LAN_WAKE_EN are in the RTC well, as the datasheet states. I can't reset RTC_EN to 0 for unknown reasons, though... wtf -- To view, visit https://review.coreboot.org/c/coreboot/+/58043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Gerrit-Change-Number: 58043 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Duncan Laurie Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 20:15:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake
by Michael Niewöhner (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Matt DeVillier, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Aaron Durbin. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58071 ) Change subject: soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58071/comment/3c875820_3718d6e2 PS7, Line 14: position. > oops, will change Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9f28cf054ae8b602c0587e4dd4a13a4aba810c7 Gerrit-Change-Number: 58071 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 20:10:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Drop SGPM, RGPM and EGPM methods
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57209 ) Change subject: soc/intel/adl: Drop SGPM, RGPM and EGPM methods ...................................................................... soc/intel/adl: Drop SGPM, RGPM and EGPM methods These methods can now be dropped as Dynamic GPIO PM is enabled. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0c7b67b5414d8c80775ab7678ce7b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57209 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/acpi/gpio.asl 1 file changed, 0 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl index 376afab..6a1ba00 100644 --- a/src/soc/intel/alderlake/acpi/gpio.asl +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -137,44 +137,3 @@ Return (Local0) } - -/* GPIO Power Management bits */ -Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0, 0}) - -/* - * Save GPIO Power Management bits - */ -Method (SGPM, 0, Serialized) -{ - For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) - { - Local1 = GPID (Local0) - GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG) - } -} - -/* - * Restore GPIO Power Management bits - */ -Method (RGPM, 0, Serialized) -{ - For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) - { - CGPM (Local0, DerefOf(GPMB[Local0])) - } -} - -/* - * Save current setting of GPIO Power Management bits and - * enable all Power Management bits for all communities - */ -Method (EGPM, 0, Serialized) -{ - /* Save current setting and will restore it when resuming */ - SGPM () - /* Enable PM bits */ - For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) - { - CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS) - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/57209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c7b67b5414d8c80775ab7678ce7b12181af7882 Gerrit-Change-Number: 57209 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/*/brya/variants/brask: Enable dynamic GPIO PM
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57443 ) Change subject: mb/*/brya/variants/brask: Enable dynamic GPIO PM ...................................................................... mb/*/brya/variants/brask: Enable dynamic GPIO PM GPIO PM was disabled for brask to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot brask to OS, ensure no TPM errors. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb 1 file changed, 0 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 646309e..76d437c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -20,17 +20,6 @@ # Enable heci communication register "HeciEnabled" = "1" - # This disabled autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # Enable CNVi BT register "CnviBtCore" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/57443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882 Gerrit-Change-Number: 57443 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/*/brya/variants/brask: Enable dynamic GPIO PM
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Meera Ravindranath. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57443 ) Change subject: mb/*/brya/variants/brask: Enable dynamic GPIO PM ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882 Gerrit-Change-Number: 57443 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 19:50:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2021