coreboot-gerrit October 2021

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Change in coreboot[master]: mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57411 ) Change subject: mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM ...................................................................... mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot adlrvp to OS, ensure no TPM timeout errors. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb 2 files changed, 0 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index cd198d5..a00ad35 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -41,16 +41,6 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - # This disabled autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # Enable PCH PCIE RP 5 using CLK 2 register "pch_pcie_rp[PCH_RP(5)]" = "{ .clk_src = 2, diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 5d24a42..1a8c641 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -10,15 +10,6 @@ device lapic 0 on end end - # This disables autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses. - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/57411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882 Gerrit-Change-Number: 57411 Gerrit-PatchSet: 4 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add CPU Crashlog PCI driver
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Francois Toguo Fotso, Furquan Shaikh, Tim Wawrzynczak, Kane Chen, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57685 ) Change subject: soc/intel/common: Add CPU Crashlog PCI driver ...................................................................... Patch Set 6: Code-Review+1 (3 comments) Patchset: PS6: Looks good, just a nit and a question. File src/soc/intel/common/block/crashlog/cpu_crashlog.c: https://review.coreboot.org/c/coreboot/+/57685/comment/bb9aded3_3a73dac3 PS6, Line 5: #include "crashlog_lib.h" nit - group of local includes follows group of system includes https://review.coreboot.org/c/coreboot/+/57685/comment/8e2cf5c3_20ed4387 PS6, Line 263: if (!is_dev_enabled(dev)) Would .init ever get called on a disabled device? -- To view, visit https://review.coreboot.org/c/coreboot/+/57685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cb61fa2570adcfe51680141ee12e0e83930bb19 Gerrit-Change-Number: 57685 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 19:47:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/alderlake: Add PsysPmax setting
by 9elements QA (Code Review) 04 Oct '21

04 Oct '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58008 ) Change subject: src/soc/intel/alderlake: Add PsysPmax setting ...................................................................... Patch Set 7: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 1 / 9 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/80615 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/80614 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/80613 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/80612 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/80611 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/80610 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/80609 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/80608 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/80607 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/58008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia07aa815f90739240f110cab984068237c02d896 Gerrit-Change-Number: 58008 Gerrit-PatchSet: 7 Gerrit-Owner: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 04 Oct 2021 19:09:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add crashlog records to BERT
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Kane Chen, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57686 ) Change subject: soc/intel/common: Add crashlog records to BERT ...................................................................... Patch Set 3: Code-Review+1 (2 comments) File src/soc/intel/common/block/acpi/acpi_bert.c: https://review.coreboot.org/c/coreboot/+/57686/comment/99484018_6310e6a3 PS3, Line 34: if (cpu_entry) This check isn't needed, it's covered on line 24. https://review.coreboot.org/c/coreboot/+/57686/comment/8e8dec6e_f1ad3af7 PS3, Line 52: if (pmc_entry) This check isn't needed, it's covered on line 24. -- To view, visit https://review.coreboot.org/c/coreboot/+/57686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I646053e00fbe4649d5fdcc7ae91dfa8477a5ae65 Gerrit-Change-Number: 57686 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 18:55:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/tcss: Optimize USB-C DP flow and code structure
by Furquan Shaikh (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang, Curtis Chen, Brandon Breitenstein. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: soc/intel/common/tcss: Optimize USB-C DP flow and code structure ...................................................................... Patch Set 22: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 22 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 18:53:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/device: Generic interface for USB-C mux operations
by Furquan Shaikh (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Derek Huang. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58002 ) Change subject: include/device: Generic interface for USB-C mux operations ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d Gerrit-Change-Number: 58002 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 18:52:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_ta...
by 9elements QA (Code Review) 04 Oct '21

04 Oct '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58084 ) Change subject: driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 1 / 9 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/80606 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/80605 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/80604 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/80603 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/80602 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/80601 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/80600 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/80599 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/80598 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/58084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd Gerrit-Change-Number: 58084 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 18:47:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi to src/lib: Fix spelling errors
by build bot (Jenkins) (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Lance Zhao, Martin Roth, Philipp Hug, Tim Wawrzynczak, Christian Walter, Angel Pons, Julius Werner, Ron Minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58080 ) Change subject: src/acpi to src/lib: Fix spelling errors ...................................................................... Patch Set 3: (1 comment) File src/device/oprom/x86emu/prim_ops.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129769): https://review.coreboot.org/c/coreboot/+/58080/comment/2e8dd06a_71e78e55 PS3, Line 2461: * will only support up to feature 1, which we set in register EAX. code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/58080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Gerrit-Change-Number: 58080 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Philipp Hug <philipp.hug(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 18:47:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: Documentation: Add OCP Mono Lake mainboard
by Felix Held (Code Review) 04 Oct '21

04 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57561 ) Change subject: Documentation: Add OCP Mono Lake mainboard ...................................................................... Documentation: Add OCP Mono Lake mainboard Add information about the OCP Mono Lake mainboard. Change-Id: I2109cca0e4037a2945bcb7e4d80897b48ada54af Signed-off-by: Marc Jones <marcjones(a)sysproconsutling.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57561 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Jay Talbott <JayTalbott(a)sysproconsulting.com> Tested-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/ocp/monolake.md 2 files changed, 150 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Verified; Looks good to me, approved Jay Talbott: Looks good to me, but someone else must approve diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 60302cb..39cd9a4 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -99,6 +99,10 @@ - [MS-7707](msi/ms7707/ms7707.md) +## OCP + +- [Mono Lake](ocp/monolake.md) + ## Open Cellular - [Elgon](opencellular/elgon.md) diff --git a/Documentation/mainboard/ocp/monolake.md b/Documentation/mainboard/ocp/monolake.md new file mode 100644 index 0000000..e825bff --- /dev/null +++ b/Documentation/mainboard/ocp/monolake.md @@ -0,0 +1,146 @@ +# OCP Mono Lake + +This page describes coreboot support status for the [OCP] (Open Compute Project) +Mono Lake server platform. + +## Introduction + +OCP Mono Lake server platform is a component of multi-host server Yosemite-V1. +Facebook [introduced Yosemite] in 2015 and the [Mono Lake was accepted] to OCP in 2019. + +Mono Lake server is a single socket BroadwellDE server. + +Yosemite-V1 may host up to 4 Mono Lake servers (blades) in one sled. + +The Yosemite-V1 system is in mass production. Facebook, Intel, ITRenew and partners +jointly develop Open System Firmware (OSF) solution on Mono Lake as an alternative +solution. The OSF solution is based on coreboot/FSP/LinuxBoot stack. A firmware binary +is available from ITRenew. + +coreboot Mono Lake is supported on the coreboot version 4.11 branch. +The Broadwell-DE FSP v1.0 support was dropped after 4.11. + + +## Required blobs + +Mono Lake server OSF solution requires: +- [FSP] blob: SysPro custom FSP is required to support the 16-core Broadwell-DE on Mono Lake +- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git +- ME binary: Available under NDA with Intel + +## Payload +- LinuxBoot: Linuxboot is the prefered coreboot payload for Mono Lake. + It can be built following [All about u-root]. + + Tested configuration: + Linux Kernel v5.10.44 + [u-root Mono Lake pull request] + u-root build command: + GO111MODULE=off u-root -build=bb -uinitcmd=systemboot \ + -files="${FLASHROMDIR}/flashrom:bin/flashrom" \ + -files="${VPDDIR}/vpd:bin/vpd" \ + core github.com/u-root/u-root/cmds/boot/{systemboot,pxeboot,boot} \ + github.com/u-root/u-root/cmds/exp/{cbmem,dmidecode,modprobe,ipmidump,netboo… \ + + note: flashrom and vpd binaries must be precompiled + +## Flashing coreboot + +Mono Lake in-band BIOS firmware image update uses [flashrom]: + flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \ + -i bios --noverify-all -w <path to coreboot image> + +Yosemite-V1 OpenBMC BIOS firmware image update uses fw-util: + fw-util slotx --update bios <path to coreboot image> + +## Yosimite-V1 server controls + +To power off/on a Mono Lake host: + power-util slotx off + power-util slotx on + +To connect to coreboot and Linux console through SOL (Serial Over Lan): + sol-util slotx + +## Firmware configurations +[ChromeOS VPD] is used to store most of the firmware configurations. +RO_VPD region holds default values, while RW_VPD region holds customized +values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses that value to populate smbios type 1 version field. +- bmc_bootorder_override: When it's set to 1 IPMI OEM command can override boot + order. The boot order override is done in the u-root LinuxBoot payload. +- systemboot_log_level: u-root package systemboot log levels, would be mapped to + quiet/verbose in systemboot as that is all we have for now. 5 to 8 would be + mapped to verbose, 0 to 4 and 9 would be mapped to quiet. +- VPDs affecting coreboot are in src/mainboard/ocp/monolake/mainboard.c. + No coreboot VPD are required, uses safe defaults. + +## Working features +The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, +and [u-root] as initramfs. +- BMC integration: + - BMC readiness check + - IPMI commands + - watchdog timer + - POST complete pin acknowledgement + - Check BMC version: ipmidump -device +- Early serial output +- ACPI tables: DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT/XSDT +- FSP MRC cache support (Skipping memory training upon subsequent reboots) +- Versions + - Check FSP version: cbmem | grep LB_TAG_PLATFORM_BLOB_VERSION + - Check Microcode version: cat /proc/cpuinfo | grep microcode +- Devices: + - Boot drive + - All 5 data drives + - NIC card +- SMBIOS: + - Type 0 – BIOS Information + - Type 1 – System Information + - Type 2 – Baseboard Information + - Type 3 – System Enclosure or Chassis + - Type 4 – Processor Information + - Type 7 – Cache Information + - Type 16 – Physical Memory Array + - Type 17 – Memory Device + - Type 32 – System Boot Information + - Type 38 – IPMI Device Information + - Type 41 – Onboard Devices Extended Information + - Type 127 – End-of-Table +- Power button +- u-root boot +- u-root pxeboot + +## Stress and Performance tests passed + +## Known issues + +### Feature gaps +- flashrom command not able to update ME region +- ACPI BERT table +- PCIe hotplug through VPP (Virtual Pin Ports) +- RO_VPD region as well as other RO regions are not write protected +- Not able to selectively enable/disable core + +## Technology + +```eval_rst ++------------------------+---------------------------------------------+ +| Processor (1 socket) | Broadwell-DE | ++------------------------+---------------------------------------------+ +| BMC | Aspeed AST 1250 | ++------------------------+---------------------------------------------+ +``` + +[OCP]: https://www.opencompute.org +[introduced Yosemite]: https://engineering.fb.com/2015/03/10/core-data/introducing-yosemite-the-fi… +[Mono Lake was accepted]: https://www.opencompute.org/contributions?query=Tioga%20Pass%20v1.0 +[FSP]: https://doc.coreboot.org/soc/intel/fsp/index.html +[u-root Mono Lake pull request]: https://github.com/u-root/u-root/pull/2045 +[flashrom]: https://flashrom.org/Flashrom +[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root +[u-root]: https://u-root.org/ +[ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md -- To view, visit https://review.coreboot.org/c/coreboot/+/57561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I2109cca0e4037a2945bcb7e4d80897b48ada54af Gerrit-Change-Number: 57561 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Enable DDR4 SODIMM for brask
by Felix Held (Code Review) 04 Oct '21

04 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56539 ) Change subject: mb/google/brya: Enable DDR4 SODIMM for brask ...................................................................... mb/google/brya: Enable DDR4 SODIMM for brask Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in brask device tree and add SPD addressese for the two DIMMs. Separate the Kconfig items of brya and brask. Move HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya and add config SPD_CACHE_IN_FMAP to brask. Add a new section RW_SPD_CACHE to fmd for caching SPD data. The renamed romstage.c is used by both brya and brask and a new function variant_get_spd_info is provided to support the different SPD source types. BUG=b:194055762 BRANCH=None TEST=build pass Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Makefile.inc M src/mainboard/google/brya/chromeos.fmd R src/mainboard/google/brya/romstage.c M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb A src/mainboard/google/brya/variants/baseboard/brask/memory.c M src/mainboard/google/brya/variants/baseboard/brya/memory.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h 9 files changed, 68 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 5f53c69..e6e44e2 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,10 +1,12 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n - select ROMSTAGE_SPD_CBFS + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select HAVE_SPD_IN_CBFS select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_BASEBOARD_BRASK def_bool n + select SPD_CACHE_IN_FMAP if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK @@ -50,7 +52,6 @@ default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK config CHROMEOS - select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH @@ -118,10 +119,6 @@ int default 0 -config ROMSTAGE_SPD_CBFS - def_bool n - select HAVE_SPD_IN_CBFS - config HAVE_WWAN_POWER_SEQUENCE def_bool n help diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index 5dabd84..c40f21c 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -3,7 +3,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c +romstage-y += romstage.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c @@ -15,7 +15,7 @@ subdirs-y += variants/baseboard/$(BASEBOARD_DIR) subdirs-y += variants/$(VARIANT_DIR) subdirs-y += variants/$(VARIANT_DIR)/memory -subdirs-$(CONFIG_ROMSTAGE_SPD_CBFS) += spd +subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd index c1a4147..9e4bfa9 100644 --- a/src/mainboard/google/brya/chromeos.fmd +++ b/src/mainboard/google/brya/chromeos.fmd @@ -21,6 +21,11 @@ SHARED_DATA 8K VBLOCK_DEV 8K } + # The RW_SPD_CACHE region is only used for brya variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 24K } diff --git a/src/mainboard/google/brya/romstage_spd_cbfs.c b/src/mainboard/google/brya/romstage.c similarity index 81% rename from src/mainboard/google/brya/romstage_spd_cbfs.c rename to src/mainboard/google/brya/romstage.c index eadc277..d50d6e8 100644 --- a/src/mainboard/google/brya/romstage_spd_cbfs.c +++ b/src/mainboard/google/brya/romstage.c @@ -5,15 +5,17 @@ #include <fsp/api.h> #include <gpio.h> #include <soc/romstage.h> +#include <string.h> void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) { const struct mb_cfg *mem_config = variant_memory_params(); bool half_populated = variant_is_half_populated(); - const struct mem_spd spd_info = { - .topo = MEM_TOPO_MEMORY_DOWN, - .cbfs_index = variant_memory_sku(), - }; + struct mem_spd spd_info; + + memset(&spd_info, 0, sizeof(spd_info)); + variant_get_spd_info(&spd_info); + const struct pad_config *pads; size_t pads_num; diff --git a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc index 6c29346..1693d2e 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 3b9acea..646309e 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -149,5 +149,6 @@ end end device ref hda on end + device ref smbus on end end end diff --git a/src/mainboard/google/brya/variants/baseboard/brask/memory.c b/src/mainboard/google/brya/variants/baseboard/brask/memory.c new file mode 100644 index 0000000..2e24110 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/brask/memory.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {50, 20, 25, 25, 25}, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = 1, + }, +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &ddr4_mem_config; +} + +bool __weak variant_is_half_populated(void) +{ + return false; +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_DIMM_MODULE; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[1].addr_dimm[0] = 0x52; +} diff --git a/src/mainboard/google/brya/variants/baseboard/brya/memory.c b/src/mainboard/google/brya/variants/baseboard/brya/memory.c index 2a0b6ac..f04c97e 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/memory.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/memory.c @@ -95,3 +95,9 @@ /* GPIO_MEM_CH_SEL GPP_E13 */ return gpio_get(GPP_E13); } + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index a2c1b42..3e0fd05 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -19,6 +19,7 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num); const struct mb_cfg *variant_memory_params(void); +void variant_get_spd_info(struct mem_spd *spd_info); int variant_memory_sku(void); bool variant_is_half_populated(void); void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config); -- To view, visit https://review.coreboot.org/c/coreboot/+/56539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Gerrit-Change-Number: 56539 Gerrit-PatchSet: 17 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2021