coreboot-gerrit October 2021

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Change in coreboot[master]: soc/intel/common: Add PMC Crashlog PCI driver
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Francois Toguo Fotso, Tim Wawrzynczak, Kane Chen, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57684 ) Change subject: soc/intel/common: Add PMC Crashlog PCI driver ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/crashlog/pmc_crashlog.c: https://review.coreboot.org/c/coreboot/+/57684/comment/9b951a0f_5471f534 PS6, Line 233: copy_dwords_from_sram(table_addr, dest, crashlog_info.table.total_size); nit - blank line between declarations and first line of code -- To view, visit https://review.coreboot.org/c/coreboot/+/57684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc27bbdf35fcd680be224ba0a0e642c94d29bca3 Gerrit-Change-Number: 57684 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 18:04:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/alderlake: Add PsysPmax setting
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58008 ) Change subject: src/soc/intel/alderlake: Add PsysPmax setting ...................................................................... src/soc/intel/alderlake: Add PsysPmax setting This patch feeds PsysPmax setting to FSP through UPD and adds a PsysPmax member in chip information so that we can set PsysPmax through devicetree. The PsysPmax needs to be set correctly mapping to maximum system power. Otherwise, system performance would be limited due to the default PsysPmax setting in FSP is only 21W. BUG=b:193864533, b:195615830 TEST=Set PsysPmax to an example value eg 145 in devicetree && put debug code in FSP to print the PsysPmax value before sending to Pcode, ensure the setting is correctly programmed. Change-Id: Ia07aa815f90739240f110cab984068237c02d896 Signed-off-by: Ryan Lin <ryan.lin(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 3192478..270400b 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -492,6 +492,9 @@ POWER_CYCLE_DURATION_3S, POWER_CYCLE_DURATION_4S, } pch_reset_power_cycle_duration; + + /* Platform Power Pmax */ + uint16_t PsysPmax; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8003471..4ae2537 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -652,6 +652,13 @@ s_cfg->PchPmSlpS3MinAssert, s_cfg->PchPmSlpAMinAssert, power_cycle_duration); + + /* Set PsysPmax if it is available from DT */ + if (config->PsysPmax) { + printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax); + /* PsysPmax is in unit of 1/8 Watt */ + s_cfg->PsysPmax = config->PsysPmax * 8; + } } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/58008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia07aa815f90739240f110cab984068237c02d896 Gerrit-Change-Number: 58008 Gerrit-PatchSet: 7 Gerrit-Owner: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: merged

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Change in coreboot[master]: src/soc/intel/alderlake: Add PsysPmax setting
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Hou-hsun Lee, Ryan Lin, Kane Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58008 ) Change subject: src/soc/intel/alderlake: Add PsysPmax setting ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia07aa815f90739240f110cab984068237c02d896 Gerrit-Change-Number: 58008 Gerrit-PatchSet: 6 Gerrit-Owner: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 17:45:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/device: Generic interface for USB-C mux operations
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Derek Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58002 ) Change subject: include/device: Generic interface for USB-C mux operations ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d Gerrit-Change-Number: 58002 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 17:44:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/tcss: Optimize USB-C DP flow and code structure
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Paul Menzel, Derek Huang, Curtis Chen, Brandon Breitenstein. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: soc/intel/common/tcss: Optimize USB-C DP flow and code structure ...................................................................... Patch Set 22: (2 comments) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/57139/comment/b2ae24da_f808302c PS22, Line 297: port_bitmask = ops->dp_ops.wait_for_connection(WAIT_FOR_DISPLAYPORT_TIMEOUT_MS); suggestion: after getting `ops`, return early if ops is NULL https://review.coreboot.org/c/coreboot/+/57139/comment/e75bb0dc_41dad844 PS22, Line 331: if (ret) : printk(BIOS_ERR, "Port C%zd mux set failed with error %d\n", i, ret); : else { : printk(BIOS_INFO, "Port C%zd is configured to DP mode!\n", i); : return; : } style: if one arm of a conditional requires braces, then all branches should have them -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 22 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 17:44:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Add new API for USB-C mux handling
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Derek Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58059 ) Change subject: src/ec/google/chromeec: Add new API for USB-C mux handling ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58059/comment/6cb9df6d_66664d56 PS3, Line 7: src/ nit: remove `src/` prefix -- To view, visit https://review.coreboot.org/c/coreboot/+/58059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba Gerrit-Change-Number: 58059 Gerrit-PatchSet: 3 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 17:41:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57345 to look at the new patch set (#20). Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... driver/intel/pmc_mux/conn: Add type-c port info to cbmem This change adds type-c port information for USB type-c ports to cbmem. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/drivers/intel/pmc_mux/conn/conn.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/57345/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 20 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [Test] [Do Not Merge] mb/adlrvp_m: Add hook function to return status...
by Anil Kumar K (Code Review) 04 Oct '21

04 Oct '21

Anil Kumar K has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58090 ) Change subject: [Test] [Do Not Merge] mb/adlrvp_m: Add hook function to return status EC in RW status ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/58090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07fdd0dd9a42956f386604184d894425329db592 Gerrit-Change-Number: 58090 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/adlrvp_m: Add hook function to return EC in RW status
by Anil Kumar K (Code Review) 04 Oct '21

04 Oct '21

Anil Kumar K has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58099 ) Change subject: mb/adlrvp_m: Add hook function to return EC in RW status ...................................................................... mb/adlrvp_m: Add hook function to return EC in RW status EC_IN_RW signal from EC GPIO is connected to GPIO EC7 of SOC. The function reads this GPIO to check if EC is in RW (un trusted) or RO (trusted) Branch=none Bug=none Test=Issue manual recovery and confirm DUT is entering recovery mode on ADL-M RVP Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 --- M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/adlrvp/gpio_m.c M src/mainboard/intel/adlrvp/include/baseboard/gpio.h 3 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/58099/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Gerrit-Change-Number: 58099 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/adlrvp_m: Add hook function to return EC in RW status
by Anil Kumar K (Code Review) 04 Oct '21

04 Oct '21

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58099 ) Change subject: mb/adlrvp_m: Add hook function to return EC in RW status ...................................................................... mb/adlrvp_m: Add hook function to return EC in RW status EC_IN_RW signal from EC GPIO is connected to GPIO EC7 of SOC. The function reads this GPIO to check if EC is in RW (un trusted) or RO (trusted) Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 --- M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/adlrvp/gpio_m.c M src/mainboard/intel/adlrvp/include/baseboard/gpio.h 3 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/58099/1 diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index d963c73..15fc32f 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -12,7 +12,7 @@ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {-1, ACTIVE_HIGH, 0, "EC in RW"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } @@ -44,3 +44,9 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 6f0568d..96a137b 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -90,6 +90,9 @@ /* D9 : WWAN_FCP_POWER_OFF_N */ PAD_CFG_GPO(GPP_D9, 1, PLTRST), + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* H0 : PCH_SSD_RST# */ PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* H13 : CPU_SSD_RST# */ diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h index de0adf6..c6d1217 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h @@ -12,4 +12,6 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +#define GPIO_EC_IN_RW GPP_E7 + #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Gerrit-Change-Number: 58099 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2021