coreboot-gerrit October 2021

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Patrick Rudolph. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57345 ) Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... Patch Set 19: (1 comment) File src/drivers/intel/pmc_mux/conn/conn.c: https://review.coreboot.org/c/coreboot/+/57345/comment/34fd8256_85a3cd0a PS18, Line 46: printk(BIOS_ERR, "ERROR: No space for Type-C port info!\n"); > That is an excellent point. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 19 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 17:17:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_ta...
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58084 ) Change subject: driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h ...................................................................... driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h Move the locally declared typec_orientation enum from chip.h to coreboot_tables.h. Change enum typec_orientation name to type_c_orientation for consistency with contents of coreboot_tables.h. Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE. BUG=b:149830546 TEST="emerge-volteer coreboot" and make sure it compiles successfully. Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c 4 files changed, 25 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Furquan Shaikh: Looks good to me, approved diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index a841e03..914cfa5 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -143,6 +143,12 @@ u8 strings[0]; }; +enum type_c_orientation { + TYPEC_ORIENTATION_NONE, + TYPEC_ORIENTATION_NORMAL, + TYPEC_ORIENTATION_REVERSE, +}; + struct type_c_port_info { /* * usb2_port_number and usb3_port_number are expected to be diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index ab8da7b..91da8e0 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -426,7 +426,17 @@ * USB Type-C Port Information * This record contains board-specific type-c port information. * There will be one record per type-C port. + * Orientation fields should be of type enum type_c_orientation. */ +enum type_c_orientation { + /* The orientation of the signal follows the orientation of the CC lines. */ + TYPEC_ORIENTATION_NONE, + /* The orientation of the signal is fixed to follow CC1 */ + TYPEC_ORIENTATION_NORMAL, + /* The orientation of the signal is fixed to follow CC2 */ + TYPEC_ORIENTATION_REVERSE, +}; + struct type_c_port_info { uint8_t usb2_port_number; uint8_t usb3_port_number; diff --git a/src/drivers/intel/pmc_mux/conn/chip.h b/src/drivers/intel/pmc_mux/conn/chip.h index 461916e..96347ae 100644 --- a/src/drivers/intel/pmc_mux/conn/chip.h +++ b/src/drivers/intel/pmc_mux/conn/chip.h @@ -3,14 +3,7 @@ #ifndef __DRIVERS_INTEL_PMC_MUX_CONN_H__ #define __DRIVERS_INTEL_PMC_MUX_CONN_H__ -enum typec_orientation { - /* The orientation of the signal follows the orientation of the CC lines. */ - TYPEC_ORIENTATION_FOLLOW_CC = 0, - /* The orientation of the signal is fixed to follow CC1 */ - TYPEC_ORIENTATION_NORMAL, - /* The orientation of the signal is fixed to follow CC2 */ - TYPEC_ORIENTATION_REVERSE, -}; +#include <boot/coreboot_tables.h> struct drivers_intel_pmc_mux_conn_config { /* 1-based port numbers (from SoC point of view) */ @@ -18,9 +11,9 @@ /* 1-based port numbers (from SoC point of view) */ int usb3_port_number; /* Orientation of the sideband signals (SBU) */ - enum typec_orientation sbu_orientation; + enum type_c_orientation sbu_orientation; /* Orientation of the High Speed lines */ - enum typec_orientation hsl_orientation; + enum type_c_orientation hsl_orientation; }; /* diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index b6bf371..7a622c8 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpigen.h> +#include <boot/coreboot_tables.h> #include <console/console.h> #include <intelblocks/acpi.h> + #include "chip.h" static const char *conn_acpi_name(const struct device *dev) @@ -12,14 +14,14 @@ return name; } -static const char *orientation_to_str(enum typec_orientation ori) +static const char *orientation_to_str(enum type_c_orientation ori) { switch (ori) { case TYPEC_ORIENTATION_NORMAL: return "normal"; case TYPEC_ORIENTATION_REVERSE: return "reverse"; - case TYPEC_ORIENTATION_FOLLOW_CC: /* Intentional fallthrough */ + case TYPEC_ORIENTATION_NONE: /* Intentional fallthrough */ default: return ""; } @@ -52,11 +54,11 @@ * The kernel assumes that these Type-C signals (SBUs and HSLs) follow the CC lines, * unless they are explicitly called out otherwise. */ - if (config->sbu_orientation != TYPEC_ORIENTATION_FOLLOW_CC) + if (config->sbu_orientation != TYPEC_ORIENTATION_NONE) acpi_dp_add_string(dsd, "sbu-orientation", orientation_to_str(config->sbu_orientation)); - if (config->hsl_orientation != TYPEC_ORIENTATION_FOLLOW_CC) + if (config->hsl_orientation != TYPEC_ORIENTATION_NONE) acpi_dp_add_string(dsd, "hsl-orientation", orientation_to_str(config->hsl_orientation)); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd Gerrit-Change-Number: 58084 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Nico Huber, Nick Vaccaro, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57345 to look at the new patch set (#19). Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... driver/intel/pmc_mux/conn: Add type-c port info to cbmem This change adds type-c port information for USB type-c ports to cbmem. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/drivers/intel/pmc_mux/conn/conn.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/57345/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 19 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... coreboot tables: Add type-c port info to coreboot table This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 54 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 91f8486..a841e03 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -82,6 +82,7 @@ CB_TAG_SMMSTOREV2 = 0x0039, CB_TAG_BOARD_CONFIG = 0x0040, CB_TAG_ACPI_CNVS = 0x0041, + CB_TAG_TYPE_C_INFO = 0x0042, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, @@ -142,6 +143,27 @@ u8 strings[0]; }; +struct type_c_port_info { + /* + * usb2_port_number and usb3_port_number are expected to be + * the port numbers as seen by the USB controller in the SoC. + */ + uint8_t usb2_port_number; + uint8_t usb3_port_number; + + /* + * Valid sbu_orientation and data_orientation values will be of + * type enum type_c_orienation. + */ + uint8_t sbu_orientation; + uint8_t data_orientation; +}; + +struct type_c_info { + u32 port_count; + struct type_c_port_info port_info[0]; +}; + struct cb_string { u32 tag; u32 size; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 26dece7..b34476d 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -148,6 +148,8 @@ #if CONFIG(LP_PCI) struct pci_access pacc; #endif + /* USB Type-C Port Configuration Info */ + uintptr_t type_c_info; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 269275d..bd10411 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -246,6 +246,11 @@ info->fmap_cache = get_cbmem_addr(ptr); } +static void cb_parse_type_c_info(void *ptr, struct sysinfo_t *info) +{ + info->type_c_info = get_cbmem_addr(ptr); +} + #if CONFIG(LP_TIMER_RDTSC) static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) { @@ -420,6 +425,9 @@ case CB_TAG_FMAP: cb_parse_fmap_cache(ptr, info); break; + case CB_TAG_TYPE_C_INFO: + cb_parse_type_c_info(ptr, info); + break; default: cb_parse_arch_specific(rec, info); break; diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index d251a4e..a9cf7bd 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -78,6 +78,7 @@ #define CBMEM_ID_CBFS_RW_MCACHE 0x574d5346 #define CBMEM_ID_FSP_LOGO 0x4c4f474f #define CBMEM_ID_SMM_COMBUFFER 0x53534d32 +#define CBMEM_ID_TYPE_C_INFO 0x54595045 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -145,5 +146,6 @@ { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ { CBMEM_ID_FMAP, "FMAP "}, \ { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ - { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "} + { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \ + { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"} #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index fd7461d5..ab8da7b 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -84,6 +84,7 @@ LB_TAG_TPM_PPI_HANDOFF = 0x003a, LB_TAG_BOARD_CONFIG = 0x0040, LB_TAG_ACPI_CNVS = 0x0041, + LB_TAG_TYPE_C_INFO = 0x0042, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, @@ -421,6 +422,23 @@ int32_t early_cmd1_status; }; +/* + * USB Type-C Port Information + * This record contains board-specific type-c port information. + * There will be one record per type-C port. + */ +struct type_c_port_info { + uint8_t usb2_port_number; + uint8_t usb3_port_number; + uint8_t sbu_orientation; + uint8_t data_orientation; +}; + +struct type_c_info { + uint32_t port_count; + struct type_c_port_info port_info[0]; +}; + struct lb_macs { uint32_t tag; uint32_t size; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 27f5315..d0cba80 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -252,6 +252,7 @@ {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG}, {CBMEM_ID_FMAP, LB_TAG_FMAP}, {CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF}, + {CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO}, }; int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 33 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 04 Oct '21

04 Oct '21

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... Patch Set 32: (2 comments) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57069/comment/ddab74b4_aaeb0b91 PS27, Line 431: enum type_c_orientation { > I like the idea of adding the enum in a follow-up. […] I split it out into 58084 (see new dependency chain). File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/57069/comment/987878f7_bfd8cbb5 PS8, Line 99: struct drivers_intel_pmc_mux_conn_config *config = child->chip_info; : if (config) { : info[count].usb2_port_number = config->usb2_port_number; : info[count].usb3_port_number = config->usb3_port_number; : info[count].sbu_orientation = config->sbu_orientation; : info[count].data_orientation = config->hsl_orientation; : count++; : } > Is the new conn_get_type_c_list() sufficient for that purpose? If not, are there additional checks […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 32 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 16:51:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/hardwaremain: change type of "complete" element in boot_state struct
by 9elements QA (Code Review) 04 Oct '21

04 Oct '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58076 ) Change subject: lib/hardwaremain: change type of "complete" element in boot_state struct ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 1 / 9 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/80587 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/80586 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/80585 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/80584 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/80583 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/80582 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/80581 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/80580 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/80579 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/58076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd Gerrit-Change-Number: 58076 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 16:31:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/hardwaremain: add missing types.h include
by 9elements QA (Code Review) 04 Oct '21

04 Oct '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58075 ) Change subject: lib/hardwaremain: add missing types.h include ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 1 / 9 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/80578 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/80577 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/80576 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/80575 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/80574 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/80573 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/80572 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/80571 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/80570 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/58075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd67aff9eba01f9618004c869f1473217b3aeae4 Gerrit-Change-Number: 58075 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 16:23:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization
by John Zhao (Code Review) 04 Oct '21

04 Oct '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58098 ) Change subject: soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization ...................................................................... soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency optimization. This change adds additional ACPI DSM function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the USB4/TBT topology which has the same implementation on Tiger Lake in commit I5a19118b75ed0a78b7436f2f90295c03928300d7. BUG=b:199757442 TEST= To be validated on Alder Lake platform board. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I0c8977c96de27ab0e554469eba658660975b8493 --- M src/soc/intel/alderlake/acpi/tcss_pcierp.asl 1 file changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58098/1 diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 589a3e9..799c0ce 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -1,5 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency + * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream + * port of the USB4/TBT topology. + */ +/* Number of microseconds to wait after a conventional reset */ +#define FW_RESET_TIME 50000 + +/* Number of microseconds to wait after data link layer active report */ +#define FW_DL_UP_TIME 1 + +/* Number of microseconds to wait after a function level reset */ +#define FW_FLR_RESET_TIME 1 + +/* Number of microseconds to wait from D3 hot to D0 transition */ +#define FW_D3HOT_TO_D0_TIME 50000 + +/* Number of microseconds to wait after setting the VF enable bit */ +#define FW_VF_ENABLE_TIME 1 + OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) Field (PXCS, AnyAcc, NoLock, Preserve) { @@ -64,10 +84,49 @@ Return (Buffer() { 0x00 }) } +/* + * A bitmask of functions support + */ +Name(OPTS, Buffer(2) {0, 0}) + Device (PXSX) { Name (_ADR, 0x00000000) + /* + * _DSM Device Specific Method + * + * Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D + * Arg1: Revision ID: 3 + * Arg2: Function index: 0, 9 + * Arg3: Empty package + */ + Method (_DSM, 4, Serialized) + { + If (Arg0 == ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) { + If (Arg1 >= 3) { + If (Arg2 == 0) { + /* + * Function index: 0 + * Standard query - A bitmask of functions supported + */ + CreateBitField(OPTS, 9, FUN9) + FUN9 = 1 + Return (OPTS) + } ElseIf (Arg2 == 9) { + /* + * Function index: 9 + * Specifying device readiness durations + */ + Return (Package() { FW_RESET_TIME, FW_DL_UP_TIME, + FW_FLR_RESET_TIME, FW_D3HOT_TO_D0_TIME, + FW_VF_ENABLE_TIME }) + } + } + } + Return (Buffer() { 0x0 }) + } + Method (_PRW, 0) { Return (Package() { 0x69, 4 }) -- To view, visit https://review.coreboot.org/c/coreboot/+/58098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c8977c96de27ab0e554469eba658660975b8493 Gerrit-Change-Number: 58098 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Implement __weak smihandler_soc_disable_busmaster
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Kane Chen, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58093 ) Change subject: soc/intel/common: Implement __weak smihandler_soc_disable_busmaster ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Kane, my only concern is cnl, ekl, icl, skl, xeon_sp. Is the PMC BME bit required for these other platforms too? -- To view, visit https://review.coreboot.org/c/coreboot/+/58093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ed7e6a3f60588bfb90481ea493495080dbbfd58 Gerrit-Change-Number: 58093 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 16:19:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Skip setting D0I3 bit for HECI devices
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57815 ) Change subject: soc/intel/alderlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 9: Code-Review+2 (1 comment) Patchset: PS9: Thanks Subrata! -- To view, visit https://review.coreboot.org/c/coreboot/+/57815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86d61c49b8f187611efd495712ad901184665f31 Gerrit-Change-Number: 57815 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 16:16:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2021