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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 76:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/52800/comment/460a05a1_125b8d5c
PS74, Line 998: set_uint_option("me_state_counter", me_state_counter);
> What could cause it to fail?
The implementation in `src/drivers/pc80/rtc/option.c` has several checks that can return an error, but they aren't an issue here.
I'd be more concerned about this with other option implementations, but currently only CMOS exists. The issue would happen with all `set_uint_option()` calls, so nothing to do here.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58065 )
Change subject: mb/prodrive/hermes: Fix PCIe ClkSrc configuration
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58065/comment/ff78c778_bd93e2f1
PS2, Line 10: Apparently, FSP does not turn off unused PCIe clock sources when using
> That could be, but I still don't get why this is mentioned as the ClkSrc configuration ist invalid f […]
Yes, the ClkSrc configuration in FSP UPDs is wrong. However, it wasn't noticed until now because the clock sources don't get disabled when running SPS firmware. After trying to use CSME firmware, the issue became apparent.
I can omit this reasoning if it's not necessary.
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Change subject: drivers/intel/fsp2_0: don't force-use `python2`
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/drivers/intel/fsp2_0/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58088/comment/a09f204a_0d7162cb
PS2, Line 81: python2
> Hm, maybe python3 though?
If the script supports both versions, I think `python` is more flexible. Even though no one should use a system with only python2 and without python3.
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Change subject: drivers/intel/fsp2_0: don't force-use `python2`
......................................................................
Patch Set 2:
(1 comment)
This change is ready for review.
File src/drivers/intel/fsp2_0/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58088/comment/41d81144_e8b7ef3e
PS2, Line 81: python2
> Hm, maybe python3 though?
no, that's creating the same problem we have now; just use what is there
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Change subject: soc/intel: deduplicate acpi_fill_soc_wake
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/58043/comment/bed03821_53ca5da1
PS1, Line 220: RTC_EN
> > So, *is* RTC alway-on? Doesn't seem to
>
> According to the datasheets it is not. There is still the rumor around that
> some bits would be in the wrong power well. I think we should confirm that
> for each bit in question before making assumptions.
>
> Even if an EN bit that controls a wake event would be cleared during suspend,
> simply assuming it was set won't fix things. It's a bit; if we don't know
> what value it had (OS sets the value), chances are 50% to be wrong either
> way.
>
> I guess, if this power-well oddity exists at all, the correct way to deal
> with it would be to capture the EN state when suspending. (An actual
> use-case for GNVS?)
I already tested this for the Deep Sx registers. They are, as the datasheet says, in the RTC powerwell.
I will test LAN_WAKE_EN, RTC_EN later
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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58079/comment/20c1b2db_15b98192
PS2, Line 10: unsupported in the FADT.
> > > Not sure about p_lvl3_lat, since C3 is supported at least on SKL […]
see CB:58096
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Hello Felix Singer, build bot (Jenkins), Furquan Shaikh, Benjamin Doron, Matt DeVillier, Paul Menzel, Mimoja, Angel Pons, Subrata Banik, Arthur Heymans, Kyösti Mälkki, Matthew Garrett, Patrick Rudolph, Aaron Durbin, Tim Crawford, Nico Huber, Tim Wawrzynczak, Maxim Polyakov, Michal Zygowski, Wim Vervoorn,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#16).
Change subject: soc/intel/skylake: switch to common ACPI code
......................................................................
soc/intel/skylake: switch to common ACPI code
Use the common ACPI code to reduce code duplication.
Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/supermicro/x11-lga1151-series/fadt.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/fadt.c
D src/soc/intel/skylake/include/soc/acpi.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/include/soc/pmc.h
M src/soc/intel/skylake/include/soc/ramstage.h
9 files changed, 62 insertions(+), 423 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44138/16
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