coreboot-gerrit October 2021

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Change in coreboot[master]: tests: Add lib/lzma-test test case
by Paul Menzel (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57555 ) Change subject: tests: Add lib/lzma-test test case ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57555/comment/f7a412e3_64bf2711 PS1, Line 8: > > It would show, that two(?) new tests are added […] Thank you. As written, for me that would make it obvious that the test consists of six test cases, and in the future, users running the tests would have something to compare to. -- To view, visit https://review.coreboot.org/c/coreboot/+/57555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id75e0b41991382d4c391b031862106de58eacdf7 Gerrit-Change-Number: 57555 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 16:08:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Don't send CSE EOP if CSME is disabled
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Sean Rhodes, Furquan Shaikh, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57149 ) Change subject: soc/intel: Don't send CSE EOP if CSME is disabled ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic00fdb0d97fefac977c0878d1d5893d07d4481ea Gerrit-Change-Number: 57149 Gerrit-PatchSet: 19 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 16:06:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Improve x86_64
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Patrick Rudolph, Paul Menzel, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56017 ) Change subject: Documentation: Improve x86_64 ...................................................................... Patch Set 6: Code-Review+1 (2 comments) File Documentation/arch/x86/x86_64.md: https://review.coreboot.org/c/coreboot/+/56017/comment/842623b8_552d669d PS6, Line 35: coreboot's `coreboot` https://review.coreboot.org/c/coreboot/+/56017/comment/1bc196e4_7773154b PS6, Line 112: Until now it could be verified on various Intel platforms and no issues have : been found. This sentence isn't very clear. It *could* be verified, and it was? or it could and no issues have been found b/c no one tried? -- To view, visit https://review.coreboot.org/c/coreboot/+/56017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855 Gerrit-Change-Number: 56017 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 16:04:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: *x86: remove lapic_read_around
by Julian Stecklina (Code Review) 04 Oct '21

04 Oct '21

Julian Stecklina has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58097 ) Change subject: *x86: remove lapic_read_around ...................................................................... *x86: remove lapic_read_around This macro has been a plain wrapper around lapic_read for a long time and there seems to be no discernable reason to have a different variant of lapic_read. This commit carries no functional change. Change-Id: Ib2d2e9054be65a8a061306db2a3b77f56f764f82 Signed-off-by: Julian Stecklina <julian.stecklina(a)cyberus-technology.de> --- M src/cpu/x86/lapic/lapic.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/lapic.h 3 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/58097/1 diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index a5b4cd5..db4a959 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -22,14 +22,14 @@ * Set Task Priority to 'accept all'. */ lapic_write_around(LAPIC_TASKPRI, - lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK); + lapic_read(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK); /* Put the local APIC in virtual wire mode */ lapic_write_around(LAPIC_SPIV, - (lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK)) + (lapic_read(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE); lapic_write_around(LAPIC_LVT0, - (lapic_read_around(LAPIC_LVT0) & + (lapic_read(LAPIC_LVT0) & ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | @@ -38,7 +38,7 @@ LAPIC_DELIVERY_MODE_EXTINT) ); lapic_write_around(LAPIC_LVT1, - (lapic_read_around(LAPIC_LVT1) & + (lapic_read(LAPIC_LVT1) & ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index f89d9e3..122d2ff 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -165,7 +165,7 @@ for (j = 1; j <= CONFIG_NUM_IPI_STARTS; j++) { printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid); - lapic_read_around(LAPIC_SPIV); + lapic_read(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); lapic_read(LAPIC_ESR); printk(BIOS_SPEW, "After apic_write.\n"); @@ -205,7 +205,7 @@ * Due to the Pentium erratum 3AP. */ if (maxlvt > 3) { - lapic_read_around(LAPIC_SPIV); + lapic_read(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); } accept_status = (lapic_read(LAPIC_ESR) & 0xEF); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 717fc9a..a548919 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -120,7 +120,6 @@ : : "memory", "cc"); } -# define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) void lapic_virtual_wire_mode_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/58097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2d2e9054be65a8a061306db2a3b77f56f764f82 Gerrit-Change-Number: 58097 Gerrit-PatchSet: 1 Gerrit-Owner: Julian Stecklina Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/hardwaremain: change type of "complete" element in boot_state struct
by Felix Held (Code Review) 04 Oct '21

04 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58076 ) Change subject: lib/hardwaremain: change type of "complete" element in boot_state struct ...................................................................... lib/hardwaremain: change type of "complete" element in boot_state struct A signed bitfield with a length of 1 bit can only have the values 0 and -1. Assigning a 1 ends up behaving as expected, but it's not the semantically correct thing to do there. Changing the type of the element to an unsigned bitfield with a length of 1 would fix that, but since this is used as a boolean value, just change it to bool type. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58076 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/hardwaremain.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index cb45903..fe8e53f 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -56,7 +56,7 @@ boot_state_t (*run_state)(void *arg); void *arg; int num_samples; - int complete : 1; + bool complete; }; #define BS_INIT(state_, run_func_) \ @@ -67,7 +67,7 @@ .phases = { { NULL, 0 }, { NULL, 0 } }, \ .run_state = run_func_, \ .arg = NULL, \ - .complete = 0, \ + .complete = false, \ } #define BS_INIT_ENTRY(state_, run_func_) \ [state_] = BS_INIT(state_, run_func_) @@ -367,7 +367,7 @@ bs_sample_time(state); - state->complete = 1; + state->complete = true; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/58076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd Gerrit-Change-Number: 58076 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/hardwaremain: add missing types.h include
by Felix Held (Code Review) 04 Oct '21

04 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58075 ) Change subject: lib/hardwaremain: add missing types.h include ...................................................................... lib/hardwaremain: add missing types.h include The u8 type is used in the file, but neither stdint.h not types.h was included in the file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifd67aff9eba01f9618004c869f1473217b3aeae4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58075 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/hardwaremain.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 2f782e7..cb45903 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -23,6 +23,7 @@ #include <thread.h> #include <timer.h> #include <timestamp.h> +#include <types.h> #include <vendorcode/google/chromeos/gnvs.h> #include <version.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/58075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd67aff9eba01f9618004c869f1473217b3aeae4 Gerrit-Change-Number: 58075 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: driver/intel/pmc_mux/conn: Add type-c port info to cbmem
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Nico Huber, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57345 ) Change subject: driver/intel/pmc_mux/conn: Add type-c port info to cbmem ...................................................................... Patch Set 18: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Gerrit-Change-Number: 57345 Gerrit-PatchSet: 18 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 15:54:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: mark C-state C2 as insupported in FADT
by Angel Pons (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58079 ) Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58079/comment/29c22ab3_0bada5d5 PS2, Line 10: unsupported in the FADT. > see CB:58096 Looks like APL and Xeon-SP properly enable I/O MWAIT redirection. -- To view, visit https://review.coreboot.org/c/coreboot/+/58079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbf770941dbdf757e7189e999d222a72412002d Gerrit-Change-Number: 58079 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 04 Oct 2021 15:49:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Tim Wawrzynczak (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... Patch Set 32: Code-Review+2 (2 comments) File src/commonlib/include/commonlib/cbmem_id.h: PS31: > This is actually required for coreboot_table.c in this CL. Ack File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/57069/comment/f3451f71_3860469d PS8, Line 99: struct drivers_intel_pmc_mux_conn_config *config = child->chip_info; : if (config) { : info[count].usb2_port_number = config->usb2_port_number; : info[count].usb3_port_number = config->usb3_port_number; : info[count].sbu_orientation = config->sbu_orientation; : info[count].data_orientation = config->hsl_orientation; : count++; : } > Is the new conn_get_type_c_list() sufficient for that purpose? If not, are there additional checks […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 32 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 15:49:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Fix PCIe ClkSrc configuration
by Patrick Rudolph (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Christian Walter, Michael Niewöhner, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58065 ) Change subject: mb/prodrive/hermes: Fix PCIe ClkSrc configuration ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58065/comment/beb49606_0f4b6ed5 PS2, Line 12: firmware. > All the CLKSRCs are configured as free-running (always on), so I'm not sure what CLKREQ# has to do w […] I changed the CSME IFD to match the SPS IFD (and devicetree) and now all PCIe devices show up. Thus this change isn't required when the IFD is correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/58065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25a34816f512510640db95251a7a792c1eebe62 Gerrit-Change-Number: 58065 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 15:45:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2021