Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Matt DeVillier, Paul Menzel, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Aaron Durbin.
Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Matt DeVillier, Paul Menzel, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Aaron Durbin,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake
......................................................................
soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake
Currently, only the PM1_STS mask gets passed to `acpi_fill_soc_wake`. To
be able to override the GPE0_STS mask as well, also pass that one. To
accomplish that, pointers to the variables are passed now.
Change-Id: If9f28cf054ae8b602c0587e4dd4a13a4aba810c7
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/include/intelblocks/acpi.h
2 files changed, 10 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/58071/8
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Duncan Laurie, Angel Pons, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58043
to look at the new patch set (#4).
Change subject: soc/intel: deduplicate acpi_fill_soc_wake
......................................................................
soc/intel: deduplicate acpi_fill_soc_wake
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific
handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in
common code.
Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/elkhartlake/acpi.c
M src/soc/intel/icelake/acpi.c
M src/soc/intel/jasperlake/acpi.c
M src/soc/intel/tigerlake/acpi.c
8 files changed, 1 insertion(+), 106 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/58043/4
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58082 )
Change subject: src/soc to src/superio: Fix spelling errors.
......................................................................
Patch Set 1: Code-Review+1
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58082/comment/6aedd8a1_c06a9d6b
PS1, Line 7: .
commit summaries don't end with a period
Patchset:
PS1:
> rest looks good to me
+1
File src/soc/mediatek/mt8173/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/58082/comment/cc917df9_369da76d
PS1, Line 780:
> remove one space to keep this aligned
+1
File src/soc/nvidia/tegra210/Kconfig:
https://review.coreboot.org/c/coreboot/+/58082/comment/a5db9aa9_55872dd8
PS1, Line 82: addresses
> address?
+1
File src/soc/qualcomm/sc7180/display/dsi_phy.c:
https://review.coreboot.org/c/coreboot/+/58082/comment/74709d28_abec3a43
PS1, Line 26: number
> those are abbreviations for numerator and denominator, so number is probably not the right fix here
+1
https://review.coreboot.org/c/coreboot/+/58082/comment/b67c0b43_7039f52c
PS1, Line 30: (quot * (number)) + ((rem * (number)) / (denom)); \
> same here
+1
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Change subject: src/acpi to src/lib: Fix spelling errors.
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58080/comment/018049de_7c0c40ec
PS1, Line 7: .
commit summaries don't end with a period
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Change subject: src/acpi to src/lib: Fix spelling errors.
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Patchset:
PS1:
> rest looks good to me
Agreed
File src/ec/google/chromeec/ec_commands.h:
https://review.coreboot.org/c/coreboot/+/58080/comment/7c39fa1c_48e785ad
PS1, Line 2859: * kb_wake_angle: angle to wakeup AP.
> wake up instead of wakeup?
yes
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Change subject: Documentation: Fix spelling errors.
......................................................................
Patch Set 1: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58078/comment/a67dc98c_37f18c33
PS1, Line 7: .
commit summaries don't end with a period
File Documentation/mainboard/asus/p8c_ws.md:
https://review.coreboot.org/c/coreboot/+/58078/comment/154a0562_0eb49d0b
PS1, Line 59: - Complex WLM200NX (Qualcomm Atheros AR9220) in PCI slot
> this is a company name, so this shouldn't be changed
Indeed.
File Documentation/mainboard/supermicro/x9sae.md:
https://review.coreboot.org/c/coreboot/+/58078/comment/f1fbe7b1_5b49951e
PS1, Line 74: Complex
> no. […]
Indeed, Compex is a brand
File Documentation/superio/common/ssdt.md:
https://review.coreboot.org/c/coreboot/+/58078/comment/164cc6e6_27eab274
PS1, Line 53: this
grammar error, `this` should be removed
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Change subject: src/mainboard to src/security: Fix spelling errors.
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
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https://review.coreboot.org/c/coreboot/+/58081/comment/f302ce8b_1be5221a
PS1, Line 7: .
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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58079/comment/d1a4e2dc_3fc6859b
PS2, Line 10: unsupported in the FADT.
> > Not sure about p_lvl3_lat, since C3 is supported at least on SKL
>
> p_lvl2 is also supported. ACPI states don't map 1:1 to Intel's C states (at least not during the last decade). Anyway, if we don't use P_BLK, no need to
fill p_lvl*.
Perfect
> > For src/soc/intel we're not enabling that IO redirect (at least I couldn't find anything), so it's just about getting the FADT right.
>
> APL and Xeon-SP do, `git grep MSR_PMG_IO_CAPTURE_BASE`.
Ouch. I no idea why I missed that :O Thanks
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57986 )
Change subject: soc/intel/baytrail: Set GNVS DPTE via devicetree
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57986/comment/e3d61c7a_5e58e4d7
PS1, Line 10: field, as newer Intel platforms do.
> How did you test this ?
I didn't test this. The only effect is that the GNVS DPTE field is set earlier (the `soc_fill_gnvs()` function is called immediately before the `mainboard_fill_gnvs()` function), which is insignificant.
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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58079/comment/011fe7c5_b01ff1d7
PS2, Line 10: unsupported in the FADT.
> There's also the parameter to acpigen_write_processor(). I'd set it to `0`. […]
baytrail/ and braswell/ also nuts.
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