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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58079/comment/d1547ce9_aa599a7c
PS2, Line 10: unsupported in the FADT.
> tbh I was wondering, why we have PBLK at all, since we have MWAIT support. […]
P_BLK is legacy stuff and superseded by ACPI _CST, and IIRC requires enabling I/O redirection in some MSRs.
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Change subject: mb/prodrive/hermes: Fix PCIe ClkSrc configuration
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58065/comment/43debb67_931b250d
PS2, Line 10: Apparently, FSP does not turn off unused PCIe clock sources when using
> Same here; also, this doesn't make *any* sense to me tbh o.O […]
OK, this seems to be inaccurate. I think what happens is that the ICC (Integrated Clock Controller) part of the ME works differently when using CSME vs SPS firmware. I'll revise this.
https://review.coreboot.org/c/coreboot/+/58065/comment/dc3c45b8_2ce63b56
PS2, Line 12: firmware.
> It's more likely that the 1:1 mapping of "SRC$ CLKREQ#" to pin in the new IFD causes problems. […]
All the CLKSRCs are configured as free-running (always on), so I'm not sure what CLKREQ# has to do with the issue. Swapping IFDs made no difference.
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Change subject: soc/intel: deduplicate acpi_fill_soc_wake
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/58043/comment/0b0c820e_daad76f3
PS1, Line 220: RTC_EN
> It's not about the power well. Some of the _EN bits control if a wake […]
So, *is* RTC alway-on? Doesn't seem to
You're absolutely right about the naming, that's what confused my most. I'll clean that up.
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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58079/comment/1475d464_cea6d320
PS2, Line 10: unsupported in the FADT.
> Trying to figure out if this matters, it doesn't seem to. We looked […]
tbh I was wondering, why we have PBLK at all, since we have MWAIT support. so, if we don't know of any OS that needs PBLK, let's just get rid of it
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Change subject: soc/intel: deduplicate acpi_fill_soc_wake
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Patch Set 3:
(1 comment)
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/58043/comment/4f096393_7d121048
PS1, Line 220: RTC_EN
> Yes, sure, but I'm unsure if it should be dropped or not
It's not about the power well. Some of the _EN bits control if a wake
event can be triggered, some don't. In the latter case the wake event
is often always on and the _EN bit just controls SMI/SCI generation.
It's the always on bits that we want to hardcode here. Calling them
by their _EN names makes it confusing because it's not about the actual
register bits (which control something else, see above). It's about
masking _STS bits, hence I would use those names.
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Change subject: soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58071/comment/1fa515ef_9cba2867
PS7, Line 14: position.
Usually, we keep outputs first (like in an assignment, you write
the destination first).
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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/skylake/fadt.c:
https://review.coreboot.org/c/coreboot/+/58079/comment/cdac2ac3_d105a6e6
PS2, Line 49: ACPI_FADT_C2_MP_SUPPORTED
What about this?
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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
......................................................................
Patch Set 2: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58079/comment/cb12b4c9_3d7305e7
PS2, Line 7: insupported
typo: *u*nsupported
https://review.coreboot.org/c/coreboot/+/58079/comment/0b4343a9_0b6b3c70
PS2, Line 9: Kabylake
The official spelling is `Kaby Lake`. While at it, I'd avoid using a slash with this:
Skylake and Kaby Lake CPUs don't support C-state C2.
https://review.coreboot.org/c/coreboot/+/58079/comment/078cd63e_5058bdb4
PS2, Line 9: is
typo: as
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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
......................................................................
Patch Set 2:
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Commit Message:
https://review.coreboot.org/c/coreboot/+/58079/comment/865ea4ef_97ca3dc3
PS2, Line 10: unsupported in the FADT.
> The BIOS Spec says LVL2 maps to C3, though. And for this CPU C3 maintains […]
Trying to figure out if this matters, it doesn't seem to. We looked
into the P_BLK support a while ago and it's just broken; we pass
the wrong address to acpigen_write_processor(). So the related
registers couldn't be accessed anyway, even if an OS tries to (e.g.
one that doesn't know _CST).
Let's just drop what is left of P_BLK support? IIRC, we also enable/
configure some emulation, that could be dropped too then.
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