coreboot-gerrit October 2021

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Change in coreboot[master]: soc/intel/denverton_ns: Always enable SpeedStep
by Дмитрий Понаморев (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Mariusz Szafrański, Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph, King Sumo. Дмитрий Понаморев has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57669 ) Change subject: soc/intel/denverton_ns: Always enable SpeedStep ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57669/comment/c3bdb043_e2d8ae33 PS2, Line 12: > Please add that to the commit message. […] I have tested this on Intel(R) Atom(TM) CPU C3538 @ 2.10GHz. The operating system does not change the frequency. Always 800MHz. Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 4 On-line CPU(s) list: 0-3 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 NUMA node(s): 1 Vendor ID: GenuineIntel CPU family: 6 Model: 95 Model name: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz Stepping: 1 CPU MHz: 800.000 CPU max MHz: 2100,0000 CPU min MHz: 800,0000 BogoMIPS: 4200.00 Virtualization: VT-x L1d cache: 24K L1i cache: 32K L2 cache: 2048K NUMA node0 CPU(s): 0-3 Commit Message: https://review.coreboot.org/c/coreboot/+/57669/comment/b4b41274_0806857a PS3, Line 9: When SpeedStep is disabled on an Atom C3538, the maximum CPU clock : speed is limited to 800 MHz. > This is the symptom. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Gerrit-Change-Number: 57669 Gerrit-PatchSet: 4 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Oct 2021 08:57:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Дмитрий Понаморев <dponamorev(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: King Sumo <kingsumos(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Always enable SpeedStep
by Дмитрий Понаморев (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Дмитрий Понаморев, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph, King Sumo. Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph, King Sumo, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57669 to look at the new patch set (#4). Change subject: soc/intel/denverton_ns: Always enable SpeedStep ...................................................................... soc/intel/denverton_ns: Always enable SpeedStep When "SpeedStep" is disabled on an Intel Atom C3538, the maximum CPU clock speed is always 800 MHz(min CPU clock). Оperating system cannot change the frequency. Avoid this issue allow "Intel Speed step" technology for processors that do not have "Intel Turbo Boost". Signed-off-by: Dmitry Ponamorev <dponamorev(a)gmail.com> Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57669/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/57669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Gerrit-Change-Number: 57669 Gerrit-PatchSet: 4 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: cbgfx: Clear screen by sequential access
by Hung-Te Lin (Code Review) 04 Oct '21

04 Oct '21

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57104 ) Change subject: libpayload: cbgfx: Clear screen by sequential access ...................................................................... Patch Set 5: (1 comment) File payloads/libpayload/drivers/video/graphics.c: https://review.coreboot.org/c/coreboot/+/57104/comment/32eb2237_1eb10846 PS4, Line 637: memset(FB, color & 0xff, fbinfo->y_resolution * bpl); I think most people cannot identify the difference if we simply use #202020 or #21212121 ... You may quickly test if that would speed up the execution time. (the > said memcpy() is slower than the 2-for-loop code below (not related to memset in line #637). Yes I know, but I wonder if memset is much faster then the loops, no matter the old two-for-loop or your new algorithm. -- To view, visit https://review.coreboot.org/c/coreboot/+/57104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9 Gerrit-Change-Number: 57104 Gerrit-PatchSet: 5 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 08:42:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Fix PCIe ClkSrc configuration
by Arthur Heymans (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Patrick Rudolph, Christian Walter, Angel Pons, Michael Niewöhner. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58065 ) Change subject: mb/prodrive/hermes: Fix PCIe ClkSrc configuration ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25a34816f512510640db95251a7a792c1eebe62 Gerrit-Change-Number: 58065 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 08:22:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: cbgfx: Clear screen by sequential access
by Yu-Ping Wu (Code Review) 04 Oct '21

04 Oct '21

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57104 ) Change subject: libpayload: cbgfx: Clear screen by sequential access ...................................................................... Patch Set 5: (1 comment) File payloads/libpayload/drivers/video/graphics.c: https://review.coreboot.org/c/coreboot/+/57104/comment/8587caf5_f21768dd PS4, Line 637: memset(FB, color & 0xff, fbinfo->y_resolution * bpl); > Maybe the VRAM's internal mapping is different from linear addressing? […] No I don't think so. The current background color #202124 is from google material palette. To clarify, my previous comment said memcpy() is slower than the 2-for-loop code below (not related to memset in line #637). -- To view, visit https://review.coreboot.org/c/coreboot/+/57104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9 Gerrit-Change-Number: 57104 Gerrit-PatchSet: 5 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 08:18:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: cbgfx: Clear screen by sequential access
by Hung-Te Lin (Code Review) 04 Oct '21

04 Oct '21

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57104 ) Change subject: libpayload: cbgfx: Clear screen by sequential access ...................................................................... Patch Set 5: (1 comment) File payloads/libpayload/drivers/video/graphics.c: https://review.coreboot.org/c/coreboot/+/57104/comment/ec46bd64_0a96da81 PS4, Line 637: memset(FB, color & 0xff, fbinfo->y_resolution * bpl); > I don't why this becomes even slower using memcpy() on brya. See CL:3200909. Maybe the VRAM's internal mapping is different from linear addressing? Is it possible to have a background that is memset-friendly? -- To view, visit https://review.coreboot.org/c/coreboot/+/57104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9 Gerrit-Change-Number: 57104 Gerrit-PatchSet: 5 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 08:11:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/kano: Correct MIPI camera info
by Werner Zeh (Code Review) 04 Oct '21

04 Oct '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58048 ) Change subject: mb/google/brya/variants/kano: Correct MIPI camera info ...................................................................... mb/google/brya/variants/kano: Correct MIPI camera info Correct OVTI2740 information for Kano: MIPI camera CIO port, HID and Link Freq BUG=b:200974074 TEST=Build and boot on Kano camera driver is not probed before, and it can now be probed properly after this change. Signed-off-by: Lai, Jim <jim.lai(a)intel.com> Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58048 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 8802ab2..4efcdf1 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -114,7 +114,7 @@ register "cio2_num_ports" = "1" register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" - register "cio2_prt[0]" = "2" + register "cio2_prt[0]" = "1" device generic 0 on end end end @@ -310,7 +310,7 @@ device i2c 2C on end end chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI2740"" + register "acpi_hid" = ""INT3474"" register "acpi_uid" = "0" register "acpi_name" = ""CAM0"" register "chip_name" = ""Ov 2740 Camera"" @@ -320,7 +320,7 @@ register "ssdb.lanes_used" = "2" register "ssdb.link_used" = "1" register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "link_freq[0]" = "360 * MHz" register "remote_name" = ""IPU0"" #Controls -- To view, visit https://review.coreboot.org/c/coreboot/+/58048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b Gerrit-Change-Number: 58048 Gerrit-PatchSet: 4 Gerrit-Owner: Jim Lai <jim.lai(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload: cbgfx: Clear screen by sequential access
by Yu-Ping Wu (Code Review) 04 Oct '21

04 Oct '21

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57104 ) Change subject: libpayload: cbgfx: Clear screen by sequential access ...................................................................... Patch Set 5: (1 comment) File payloads/libpayload/drivers/video/graphics.c: https://review.coreboot.org/c/coreboot/+/57104/comment/b3e6284b_a6936c09 PS4, Line 637: memset(FB, color & 0xff, fbinfo->y_resolution * bpl); > Well I'm talking about combining both of these into a single case that's somewhat optimized but work […] I don't why this becomes even slower using memcpy() on brya. See CL:3200909. -- To view, visit https://review.coreboot.org/c/coreboot/+/57104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9 Gerrit-Change-Number: 57104 Gerrit-PatchSet: 5 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 07:34:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbfstool: Add support for ARM64 UefiPayload
by Paul Menzel (Code Review) 04 Oct '21

04 Oct '21

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58055 ) Change subject: util/cbfstool: Add support for ARM64 UefiPayload ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58055/comment/8936754f_0e8e7c0c PS8, Line 10: ARM SystemReady Yes, thank you. Next time, it’d be great, if you could update the commit message. The URL you linked requires the reader to go through several marketing documents. Also not all “bands” seem to require that. From page 13 from the whitepaper: > 4.3 Base Boot Requirements > The Base Boot Requirements (BBR) document specifies firmware interface requirements > that system software, like operating systems and hypervisors, can rely on. Firmware interface requirements include the following specifications: > > • UEFI specification > • ACPI specification > • SMBIOS specification > > Other Arm specifications, for example PSCI and SMCCC > The BBR also provides recipes – a recipe meaning a set of requirements – that are > tailored to the various generic operating systems: Patchset: PS9: On what board did you actually use TianoCore now, and did you run some verification suite for ARM SystemReady? -- To view, visit https://review.coreboot.org/c/coreboot/+/58055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c0c6e263bd2f518a62ff9db44d72dd31086756a Gerrit-Change-Number: 58055 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 07:31:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by Arthur Heymans (Code Review) 04 Oct '21

04 Oct '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... Patch Set 16: (1 comment) File src/arch/x86/mmu.c: https://review.coreboot.org/c/coreboot/+/30119/comment/0f64034e_92738c1f PS16, Line 335: (uint64_t *)cbmem_add(CBMEM_ID_PAGE, pages * 4 * KiB); Should this be 4K aligned? -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 16 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Oct 2021 06:43:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2021