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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58079/comment/392499c4_dacd28e5
PS2, Line 10: unsupported in the FADT.
> ah, but I guess I can do in `src/cpu/intel/speedstep/acpi. […]
cpu/intel/speedstep is only used with older platforms, I wouldn't touch that code.
About the I/O redirection thing, CB:46917 disables it on Haswell. The patch train starting with CB:55213 contains the rest of patches.
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Change subject: cpu/intel/model_206ax/acpi.c: Do not report P_BLK
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55216/comment/e62f9c69_aff266e6
PS2, Line 7: model_206ax
Looks like I made a copy-pasta error, sorry. 206ax change is CB:55215
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 )
Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 74:
(8 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/52800/comment/6850a4c3_7fa927f6
PS74, Line 998: set_uint_option("me_state_counter", me_state_counter);
Writing the option could fail, but I'm not sure how to handle this.
https://review.coreboot.org/c/coreboot/+/52800/comment/9f7f2840_c642b74c
PS74, Line 999: %d
%u
https://review.coreboot.org/c/coreboot/+/52800/comment/4c646d50_e4ea9e52
PS74, Line 1007: ;
Not needed
https://review.coreboot.org/c/coreboot/+/52800/comment/3c3db3b1_bf4e0348
PS74, Line 1020: %d
%u
https://review.coreboot.org/c/coreboot/+/52800/comment/0819362d_5fc65f0d
PS74, Line 1038: cse_is_hfs1_com_soft_temp_disable()
I'd store the result in a constant to avoid calling this function twice
https://review.coreboot.org/c/coreboot/+/52800/comment/c78894d3_a5e6804c
PS74, Line 1053: (me_state_counter != UINT_MAX) && (me_state_counter != 0)
inner braces not needed:
if (me_state_counter != UINT_MAX && me_state_counter != 0)
https://review.coreboot.org/c/coreboot/+/52800/comment/4702106b_ce444dcf
PS74, Line 1056: ;
Not needed
https://review.coreboot.org/c/coreboot/+/52800/comment/80d6a3f6_5cda072a
PS74, Line 1059: printk(BIOS_DEBUG, "HECI: Sending command to change state\n");
This message is misleading, the command was sent earlier. I'd just remove it.
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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58079/comment/39068798_f3e817dc
PS2, Line 10: unsupported in the FADT.
> hmm, looks like only a few cpus in src/cpu/intel still configure P_BLK. […]
ah, but I guess I can do in `src/cpu/intel/speedstep/acpi.c` what Angel did in commit 772c09739 and drop the fadt fields duty_offset, duty_width, p_lvl2_lat. Not sure about p_lvl3_lat, since C3 is supported at least on SKL
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Change subject: soc/intel: deduplicate acpi_fill_soc_wake
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/58043/comment/5cf6c750_538a220d
PS1, Line 222: acpi_fill_soc_wake
> Is there a need to keep this?
Ok, I see it's used later on
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Change subject: soc/intel/skl: mark C-state C2 as insupported in FADT
......................................................................
Patch Set 2:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/58079/comment/34717242_c45bbbd0
PS2, Line 10: unsupported in the FADT.
> P_BLK is legacy stuff and superseded by ACPI _CST, and IIRC requires enabling I/O redirection in som […]
hmm, looks like only a few cpus in src/cpu/intel still configure P_BLK. I have no idea, which need it and which don't
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Change subject: tests: Add lib/lzma-test test case
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Patch Set 6: Code-Review+2
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Change subject: mb/prodrive/hermes: Fix PCIe ClkSrc configuration
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58065/comment/ed3cf6c0_ab2e82d5
PS2, Line 10: Apparently, FSP does not turn off unused PCIe clock sources when using
> OK, this seems to be inaccurate. […]
That could be, but I still don't get why this is mentioned as the ClkSrc configuration ist invalid for both, isn't it?
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