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Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57333 )
Change subject: Rename ECAM-specific MMCONF Kconfigs
......................................................................
Patch Set 8:
(4 comments)
This change is ready for review.
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/57333/comment/ce65a738_d2bd2982
PS8, Line 501:
: config PCI_NO_MMIO_OPS
: bool
: default n
: help
: If this config is selected, the MMIO access for PCI config
: space is disabled.
:
Are there scenarios where this is different from !PCI_ECAM? At least the previous naming suggested that this is just the opposite of MMCONF_SUPPORT.
Can we drop this, as we are cleaning up here anyways, please? It sounds like a mistake that this ever made it into the tree.
File src/drivers/intel/fsp1_1/romstage.c:
https://review.coreboot.org/c/coreboot/+/57333/comment/43bdaf25_83f5bca1
PS8, Line 107: if (!CONFIG(PCI_NO_MMIO_OPS))
In the Kconfig we defined:
config MMCONF_BASE_ADDRESS
hex
depends on PCI_ECAM
Because of this, we should really check for (CONFIG(PCI_ECAM)) instead of !CONFIG(PCI_NO_MMIO_OPS) because that's what decides whether CONFIG_MMCONF_BASE_ADDRESS exists or not (and this is another indication that PCI_NO_MMIO_OPS should not exist at all)
File src/include/device/pci_mmio_cfg.h:
https://review.coreboot.org/c/coreboot/+/57333/comment/ed6f0849_f88a8c30
PS8, Line 28: /* this is the ECAM case
That is now obvious.
File src/soc/intel/quark/Kconfig:
https://review.coreboot.org/c/coreboot/+/57333/comment/f8cc2086_bac2bc23
PS8, Line 13: select NO_MMCONF_SUPPORT
Some chips seem to define PCI_ECAM now, and others PCI_NO_MMIO_OPS. If we are reworking this part of the code anyways, we should drop one of the two and make the other one explicit.
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Change subject: sc7280: Enable bootblock compression
......................................................................
Patch Set 51: Code-Review+2
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Change subject: soc/qualcomm: Commonize AOP firmware support
......................................................................
Patch Set 76:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49767/comment/0396caf2_490495e5
PS75, Line 7: Add
> Commonize
Done
https://review.coreboot.org/c/coreboot/+/49767/comment/862651ed_815cdf69
PS75, Line 9: Developer/Reviewer, be aware of this patch from Napali:
> Say something like: Moving AOP firmware support from qualcomm/sc7180 into qualcomm/common?
Done
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Change subject: sc7280: Enable UART driver
......................................................................
Patch Set 27:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55963/comment/6984c7e7_8151e832
PS15, Line 7: Refactor
> Enable
Done
https://review.coreboot.org/c/coreboot/+/55963/comment/7621c137_87fa84e8
PS15, Line 9: Refactor UART driver by separating
: common and SoC specific driver code.
:
> Enable common Uart driver on sc7280
Done
File src/soc/qualcomm/sc7280/Kconfig:
https://review.coreboot.org/c/coreboot/+/55963/comment/0030f1cd_5f2adaa4
PS26, Line 17: COMPRESS_BOOTBLOCK
> I think that this is supposed to go with the previous CL in the stack (CB:52131)
Done
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Change subject: sc7280: Add SHRM firmware support
......................................................................
Patch Set 76:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49392/comment/254dd46a_6e1d5ead
PS76, Line 9: SHRM is a system hardware resource manager.
: It is used to manage run time DDRSS activities.
> Please do not break lines after each sentence, and use the full textwidth of 75 characters per line.
Ack
File src/soc/qualcomm/sc7280/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/49392/comment/88502f95_e596e451
PS76, Line 110: none
> Good point. […]
if i keep CBFS_PRERAM_COMPRESSION flag, device getting crashed at romstage with below error messsage. hence, i have keep it as none.
data (compression=2)
New segment dstaddr 0x09062b00 memsize 0x8a0 srcaddr 0x1482308c filesize 0x254
Loading Segment: addr: 0x09062b00 memsz: 0x00000000000008a0 filesz: 0x0000000000000254
using LZ4
!
exception _sync_sp_el0
ELR = 0x00000000146833e0 ESR = 0x96000021
FAR = 0x0000000009062b04 SPSR = 0x2000000c
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56642
to look at the new patch set (#17).
Change subject: google/herobrine: configure gpio to detect board ID.
......................................................................
google/herobrine: configure gpio to detect board ID.
read gpio value to get board ID.
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390
---
M src/mainboard/google/herobrine/board.h
M src/mainboard/google/herobrine/boardid.c
2 files changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/56642/17
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Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner,
I'd like you to reexamine a change. Please visit
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Change subject: sc7280: Add support for USB
......................................................................
sc7280: Add support for USB
Adding snps and qmpv4 phy configs.
Adding USB addressmap for sc7280.
Use common USB driver for sc7280.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org>
Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33
---
M src/soc/qualcomm/sc7280/Kconfig
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/include/soc/addressmap.h
3 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/56092/24
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