Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49025 )
Change subject: mb/clevo/cml-u: Rework Kconfig
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Patch Set 3: Code-Review+2
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49025 )
Change subject: mb/clevo/cml-u: Rework Kconfig
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49025/3/src/mainboard/clevo/cml-u/…
File src/mainboard/clevo/cml-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/49025/3/src/mainboard/clevo/cml-u/…
PS3, Line 21: _OPTIONS
> I tried out your suggestion and I am getting this error while `git commit --amend`: […]
ugh. it is possible / Kconfig accepts it, I've just tested it, but the linter script warns for something that usually isn't a problem... anyway, we can revisit that later; thanks for trying, though
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49025 )
Change subject: mb/clevo/cml-u: Rework Kconfig
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Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49025/3/src/mainboard/clevo/cml-u/…
File src/mainboard/clevo/cml-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/49025/3/src/mainboard/clevo/cml-u/…
PS3, Line 21: _OPTIONS
> well, vboot below (and others) is also already declared
I tried out your suggestion and I am getting this error while `git commit --amend`:
Check Kconfig files for errors (lint-stable-008-kconfig): #!!!!! Error: BOARD_CLEVO_L140CU entry at src/mainboard/clevo/cml-u/Kconfig:21 has already been created outside a choice block at src/mainboard/clevo/cml-u/Kconfig.name:3.
# 1 errors
test failed
So I think this is not possible.
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Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49048 )
Change subject: soc/intel/{icl,tgl,jsl,ehl}: add LPIT support
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Patch Set 5:
> Patch Set 5:
>
> > Patch Set 5: Code-Review+1
> >
> > I didn't check JSL and EHL, but 0x193C is right on all other silicon
>
> EHL platform sample code / refcode uses it, no idea about JSL, though
From 618876 yes that's still 0x193C
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Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49044 )
Change subject: cpu/intel: add PC10 residency counter MSR
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Patch Set 2:
> Patch Set 2:
>
> > Patch Set 2: Code-Review+2
> >
> > The PC10 residency MSR is not generic,it will not apply for generation before glodmont, and start from 4th gene in core. Also not supported yet in xeon yet. But the implemented here seems okay.
>
> Oh, I missed that :S For Xeons, can it be read though (and return 0) or do we need to guard it?
Will return 0, so no need to guard at all.
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Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48951 )
Change subject: mb/google/volteer: Add GPIO to copano support
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48951/3/src/mainboard/google/volte…
File src/mainboard/google/volteer/variants/copano/gpio.c:
https://review.coreboot.org/c/coreboot/+/48951/3/src/mainboard/google/volte…
PS3, Line 189: static const struct pad_config early_gpio_table[] = {
Please add this change to this table: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/…
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Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48948 )
Change subject: mb/google/volteer: Copano: Update SPD table
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Patch Set 4: Code-Review+1
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