coreboot-gerrit January 2021

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Change in coreboot[master]: [WIP]drivers: Get rid of set_vbe_mode_info_valid
by Patrick Rudolph (Code Review) 04 Jan '21

04 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39006 ) Change subject: [WIP]drivers: Get rid of set_vbe_mode_info_valid ...................................................................... [WIP]drivers: Get rid of set_vbe_mode_info_valid Replace set_vbe_mode_info_valid with fb_new_framebuffer_info_from_edid and migrate to new header, that's independend of VBE. Change-Id: I0c145ebcf33ae0e4ff8489d4d0bc1e46869912f3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/include/edid.h M src/include/framebuffer_info.h M src/lib/edid_fill_fb.c M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/peach_pit/mainboard.c M src/northbridge/intel/i945/gma.c M src/soc/nvidia/tegra124/display.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3399/display.c 12 files changed, 21 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39006/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index fed7754..2fa1a58 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -221,7 +221,7 @@ return ret; } - /* Updated edid for set_vbe_mode_info_valid */ + /* Updated edid for fb_fill_framebuffer_info */ edid.x_resolution = edid.mode.ha; edid.y_resolution = edid.mode.va; edid.framebuffer_bits_per_pixel = format.cpp[0] * 8; diff --git a/src/include/edid.h b/src/include/edid.h index 7c3e9c8..f61a71e 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -109,8 +109,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out); void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment); -struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); -void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation); int set_display_mode(struct edid *edid, enum edid_modes mode); #endif /* EDID_H */ diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h index 6d2f9a6..a2f2b39 100644 --- a/src/include/framebuffer_info.h +++ b/src/include/framebuffer_info.h @@ -42,4 +42,7 @@ void fb_fill_framebuffer_set_orientation(struct edid_fb_info *info, enum lb_fb_orientation orientation); +struct edid_fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid, + uintptr_t fb_addr); + #endif /* __FRAMEBUFFER_INFO_H_ */ diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 1928335..d387802 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -139,7 +139,8 @@ /* * Take an edid, and create a framebuffer. Set fb_valid to 1. */ -struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) +struct edid_fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid, + uintptr_t fb_addr) { struct edid_fb_info *info = fb_new_framebuffer_info(); if (!info) diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 30f8805..0d50953 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -32,6 +32,7 @@ #include <soc/usb.h> #include <symbols.h> #include <vbe.h> +#include <framebuffer_info.h> #include "exynos5250.h" @@ -277,7 +278,7 @@ sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)fb_addr); lcd_vdd(); diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 57014b4..8b4668e 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -173,7 +173,7 @@ return false; } mtk_ddp_mode_set(edid); - struct edid_fb_info *info = set_vbe_mode_info_valid(edid, 0); + struct edid_fb_info *info = fb_new_framebuffer_info_from_edid(edid, 0); if (info) fb_fill_framebuffer_set_orientation(info, panel->s->orientation); diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 421826c..cc583fe 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -32,6 +32,7 @@ #include <soc/pll.h> #include <soc/usb.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <framebuffer_info.h> enum { CODEC_I2C_BUS = 0, @@ -238,7 +239,7 @@ } mtk_ddp_mode_set(&edid); - set_vbe_mode_info_valid(&edid, (uintptr_t)0); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); } static void mainboard_init(struct device *dev) diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 553c2ad..40947e2 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -36,6 +36,7 @@ #include <string.h> #include <symbols.h> #include <vbe.h> +#include <framebuffer_info.h> /* convenient shorthand (in MB) */ #define DRAM_START ((uintptr_t)_dram/MiB) @@ -416,7 +417,7 @@ sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)fb_addr); /* * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 98e30e7..eff0b9b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -34,6 +34,7 @@ #include <cbmem.h> #include <southbridge/intel/i82801gx/nvs.h> #include <types.h> +#include <framebuffer_info.h> #include "i945.h" #include "chip.h" @@ -386,7 +387,7 @@ (void *)pgfx, hactive * vactive * 4); memset((void *)pgfx, 0x00, hactive * vactive * 4); - set_vbe_mode_info_valid(&edid, pgfx); + fb_new_framebuffer_info_from_edid(&edid, pgfx); } else { vga_misc_write(0x67); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 6fa3bdf..e4fd183 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -27,6 +27,7 @@ #include <soc/nvidia/tegra/pwm.h> #include <stdint.h> #include <string.h> +#include <framebuffer_info.h> #include "chip.h" @@ -330,5 +331,5 @@ edid.mode.ha = config->xres; edid_set_framebuffer_bits_per_pixel(&edid, config->framebuffer_bits_per_pixel, 32); - set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); } diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index a66b2d4..fd85f8f 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -31,6 +31,7 @@ #include <soc/grf.h> #include <soc/soc.h> #include <soc/vop.h> +#include <framebuffer_info.h> #include "chip.h" @@ -138,5 +139,5 @@ break; } - set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)lcdbase); } diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 9cd4053..f76fe22 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -32,6 +32,7 @@ #include <soc/mipi.h> #include <soc/soc.h> #include <soc/vop.h> +#include <framebuffer_info.h> #include "chip.h" @@ -174,7 +175,7 @@ break; } mainboard_power_on_backlight(); - set_vbe_mode_info_valid(&edid, (uintptr_t)0); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c145ebcf33ae0e4ff8489d4d0bc1e46869912f3 Gerrit-Change-Number: 39006 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi,soc/intel/common: add support for Intel Low Power Idle Table
by Lance Zhao (Code Review) 04 Jan '21

04 Jan '21

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49045 ) Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Gerrit-Change-Number: 49045 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jan 2021 05:24:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: add SLP_S0 residency register and enable LPIT support
by Lance Zhao (Code Review) 04 Jan '21

04 Jan '21

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49047 ) Change subject: soc/intel/skl: add SLP_S0 residency register and enable LPIT support ...................................................................... Patch Set 5: Same thing, why not merge with https://review.coreboot.org/c/coreboot/+/49048? -- To view, visit https://review.coreboot.org/c/coreboot/+/49047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icccd9d15a9e9a22c9bfe7a9843e95d77013c9c8f Gerrit-Change-Number: 49047 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-Comment-Date: Mon, 04 Jan 2021 03:49:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support
by Lance Zhao (Code Review) 04 Jan '21

04 Jan '21

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49046 ) Change subject: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support ...................................................................... Patch Set 5: Why not merge with https://review.coreboot.org/c/coreboot/+/49048? -- To view, visit https://review.coreboot.org/c/coreboot/+/49046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046 Gerrit-Change-Number: 49046 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jan 2021 03:49:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support
by Lance Zhao (Code Review) 04 Jan '21

04 Jan '21

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49046 ) Change subject: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046 Gerrit-Change-Number: 49046 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jan 2021 03:47:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{icl,tgl,jsl,ehl}: add LPIT support
by Lance Zhao (Code Review) 04 Jan '21

04 Jan '21

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49048 ) Change subject: soc/intel/{icl,tgl,jsl,ehl}: add LPIT support ...................................................................... Patch Set 5: Code-Review+1 I didn't check JSL and EHL, but 0x193C is right on all other silicon -- To view, visit https://review.coreboot.org/c/coreboot/+/49048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4 Gerrit-Change-Number: 49048 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jan 2021 03:45:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel: add PC10 residency counter MSR
by Lance Zhao (Code Review) 04 Jan '21

04 Jan '21

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49044 ) Change subject: cpu/intel: add PC10 residency counter MSR ...................................................................... Patch Set 2: Code-Review+2 The PC10 residency MSR is not generic,it will not apply for generation before glodmont, and start from 4th gene in core. Also not supported yet in xeon yet. But the implemented here seems okay. -- To view, visit https://review.coreboot.org/c/coreboot/+/49044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6f74861502d4a9f872b2bbbab2e5f1925a14c4d Gerrit-Change-Number: 49044 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jan 2021 03:38:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch: set Tianocore boot timeout to 5s for PUFF-based boards
by Matt DeVillier (Code Review) 04 Jan '21

04 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48979 ) Change subject: mb/google/hatch: set Tianocore boot timeout to 5s for PUFF-based boards ...................................................................... mb/google/hatch: set Tianocore boot timeout to 5s for PUFF-based boards PUFF-based Chromeboxes need more than the 2s default in order to init an external display and show the boot splash/menu prompt. Test: build/boot WYVERN variant, ensure boot splash/menu prompt visible regardless of display init type used. Change-Id: Ie6d2151d28058501498a4c501bb221919b4e1b39 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48979/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index a4e91b6..548a8a6 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -188,4 +188,8 @@ config USE_PM_ACPI_TIMER default n +config TIANOCORE_BOOT_TIMEOUT + int + default 5 if BOARD_GOOGLE_BASEBOARD_PUFF + endif # BOARD_GOOGLE_HATCH_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/48979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6d2151d28058501498a4c501bb221919b4e1b39 Gerrit-Change-Number: 48979 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/{beltino,fizz,jecht}: Set Tianocore boot timeout to 5s
by Matt DeVillier (Code Review) 04 Jan '21

04 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48978 ) Change subject: mb/google/{beltino,fizz,jecht}: Set Tianocore boot timeout to 5s ...................................................................... mb/google/{beltino,fizz,jecht}: Set Tianocore boot timeout to 5s These Chromeboxes need more than the 2s default in order to init an external display and show the boot splash/menu prompt. Test: build/boot one of each variant, ensure boot splash/menu prompt visible regardless of display init type used. Change-Id: Ib90136b7e564451aff638af4d42abd97e42b3c19 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/jecht/Kconfig 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/48978/1 diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index cbf9dc4..9cd71a8 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -62,4 +62,8 @@ config PCIEXP_AER def_bool n +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index e09f853..548f2eb 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -99,4 +99,8 @@ config USE_PM_ACPI_TIMER default n +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + endif # BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 4851bd7..5955565 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -59,4 +59,8 @@ config PCIEXP_AER def_bool n +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib90136b7e564451aff638af4d42abd97e42b3c19 Gerrit-Change-Number: 48978 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/clevo/cml-u: Rework Kconfig
by Felix Singer (Code Review) 04 Jan '21

04 Jan '21

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49025 ) Change subject: mb/clevo/cml-u: Rework Kconfig ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/c/coreboot/+/49025/3/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/Kconfig: https://review.coreboot.org/c/coreboot/+/49025/3/src/mainboard/clevo/cml-u/… PS3, Line 13: select HAVE_SPD_IN_CBFS > are there cml-u boards without soldered ram? yes, n141cu for example. https://review.coreboot.org/c/coreboot/+/49025/3/src/mainboard/clevo/cml-u/… PS3, Line 21: _OPTIONS > nit: I don't think we really need that suffix we do, since it is already declared in Kconfig.name https://review.coreboot.org/c/coreboot/+/49025/3/src/mainboard/clevo/cml-u/… PS3, Line 21: onfig BOARD_CLEVO_L140CU_OPTIONS : bool : select BOARD_CLEVO_CMLU_COMMON : select EC_SYSTEM76_EC : select HAVE_SPD_IN_CBFS > just an idea: we could have a separate Kconfig for each variant in variants/<variant>/Kconfig where […] I thought about that, but IMO the amount of config options is too small compared to the complexity this would add. It's not worth it. So I would like to leave it just here. It's not that this file is about to explode ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/49025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f5b6f535597149f28dd8c8322acc2e988f11505 Gerrit-Change-Number: 49025 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Jan 2021 01:02:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit January 2021