coreboot-gerrit January 2021

coreboot-gerrit@coreboot.org

1 participants
6507 discussions

Change in coreboot[master]: soc/intel/baytrail/southcluster.asl: Use consistent comment formatting
by Matt DeVillier (Code Review) 05 Jan '21

05 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48746 ) Change subject: soc/intel/baytrail/southcluster.asl: Use consistent comment formatting ...................................................................... soc/intel/baytrail/southcluster.asl: Use consistent comment formatting Change-Id: I479e1eb5819c42621e8b17367b964124d5433378 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/baytrail/acpi/southcluster.asl 1 file changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48746/1 diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index f0fda15..a3417b4 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -37,118 +37,118 @@ Name (MCRS, ResourceTemplate() { - // Bus Numbers + /* Bus Numbers */ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - // IO Region 0 + /* IO Region 0 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - // PCI Config Space + /* PCI Config Space */ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - // IO Region 1 + /* IO Region 1 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - // VGA memory (0xa0000-0xbffff) + /* VGA memory (0xa0000-0xbffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, 0x00020000,,, ASEG) - // OPROM reserved (0xc0000-0xc3fff) + /* OPROM reserved (0xc0000-0xc3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, 0x00004000,,, OPR0) - // OPROM reserved (0xc4000-0xc7fff) + /* OPROM reserved (0xc4000-0xc7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, 0x00004000,,, OPR1) - // OPROM reserved (0xc8000-0xcbfff) + /* OPROM reserved (0xc8000-0xcbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, 0x00004000,,, OPR2) - // OPROM reserved (0xcc000-0xcffff) + /* OPROM reserved (0xcc000-0xcffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, 0x00004000,,, OPR3) - // OPROM reserved (0xd0000-0xd3fff) + /* OPROM reserved (0xd0000-0xd3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, 0x00004000,,, OPR4) - // OPROM reserved (0xd4000-0xd7fff) + /* OPROM reserved (0xd4000-0xd7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, 0x00004000,,, OPR5) - // OPROM reserved (0xd8000-0xdbfff) + /* OPROM reserved (0xd8000-0xdbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, 0x00004000,,, OPR6) - // OPROM reserved (0xdc000-0xdffff) + /* OPROM reserved (0xdc000-0xdffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, 0x00004000,,, OPR7) - // BIOS Extension (0xe0000-0xe3fff) + /* BIOS Extension (0xe0000-0xe3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, 0x00004000,,, ESG0) - // BIOS Extension (0xe4000-0xe7fff) + /* BIOS Extension (0xe4000-0xe7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, 0x00004000,,, ESG1) - // BIOS Extension (0xe8000-0xebfff) + /* BIOS Extension (0xe8000-0xebfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, 0x00004000,,, ESG2) - // BIOS Extension (0xec000-0xeffff) + /* BIOS Extension (0xec000-0xeffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000ec000, 0x000effff, 0x00000000, 0x00004000,,, ESG3) - // System BIOS (0xf0000-0xfffff) + /* System BIOS (0xf0000-0xfffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // LPEA Memory Region (0x20000000-0x201FFFFF) + /* LPEA Memory Region (0x20000000-0x201FFFFF) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,,, LMEM) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ DwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,,, PMEM) - // TPM Area (0xfed40000-0xfed44fff) + /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, @@ -259,7 +259,7 @@ /* IRQ routing for each PCI device */ #include "irqroute.asl" -// PCI Express Ports 0:1c.x +/* PCI Express Ports 0:1c.x */ #include "pcie.asl" Scope (\_SB) @@ -276,6 +276,6 @@ /* SCC Devices */ #include "scc.asl" - // LPE Device + /* LPE Device */ #include "lpe.asl" } -- To view, visit https://review.coreboot.org/c/coreboot/+/48746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I479e1eb5819c42621e8b17367b964124d5433378 Gerrit-Change-Number: 48746 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: soc/intel/baytrail: add LPEA resources to southcluster.asl
by Matt DeVillier (Code Review) 05 Jan '21

05 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48745 ) Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl ...................................................................... soc/intel/baytrail: add LPEA resources to southcluster.asl The LPEA device memory resources, required by Windows drivers, were not being set. Allocate required resources per Intel's Valleyview Tianocore reference code. This patch alone is not sufficient for working audio under Windows on Baytrail ChromeOS devices, but it is a necessary component. Test: boot Windows on google/swanky, observe LPEA device working properly. Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/baytrail/acpi/southcluster.asl 1 file changed, 28 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48745/1 diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index e3997d7..f0fda15 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -136,11 +136,17 @@ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + // LPEA Memory Region (0x20000000-0x201FFFFF) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PMEM) + 0x00000000,,, LMEM) + + // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + DwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PMEM) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, @@ -152,10 +158,27 @@ Method (_CRS, 0, Serialized) { + /* Update LPEA resource area */ + CreateDWordField (MCRS, ^LMEM._MIN, LMIN) + CreateDWordField (MCRS, ^LMEM._MAX, LMAX) + CreateDWordField (MCRS, ^LMEM._LEN, LLEN) + If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One))) + { + Store (LPFW, LMIN) + Store (0x00100000, LLEN) + Subtract (Add (LMIN, LLEN), One, LMAX) + } + Else + { + Store (Zero, LMIN) + Store (Zero, LMAX) + Store (Zero, LLEN) + } + /* Update PCI resource area */ - CreateDwordField(MCRS, ^PMEM._MIN, PMIN) - CreateDwordField(MCRS, ^PMEM._MAX, PMAX) - CreateDwordField(MCRS, ^PMEM._LEN, PLEN) + CreateDWordField (MCRS, ^PMEM._MIN, PMIN) + CreateDWordField (MCRS, ^PMEM._MAX, PMAX) + CreateDWordField (MCRS, ^PMEM._LEN, PLEN) /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN) -- To view, visit https://review.coreboot.org/c/coreboot/+/48745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5 Gerrit-Change-Number: 48745 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: arch/x86: Move .id section higher
by Kyösti Mälkki (Code Review) 05 Jan '21

05 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48499 ) Change subject: arch/x86: Move .id section higher ...................................................................... arch/x86: Move .id section higher The (now removed) ID_SECTION_OFFSET=0x80 was actually the secondary address flashrom and FILO are looking for. The primary was 0x10, just below .reset. If .id does not collide with .fit_pointer, use the higher of the two locations. Change-Id: I0d3a58c82efd3bbf94f4bc80ec5bbc97d5b1c109 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/bootblock.ld 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/48499/1 diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index ad9c2ef..3a4dae7 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -19,14 +19,17 @@ .id (.): { KEEP(*(.id)); } - _ID_SECTION = 0xffffff80 - SIZEOF(.id); + _ID_SECTION_END = SIZEOF(.fit_pointer) && SIZEOF(.id) > 0x28 ? 0xffffff80 : _X86_RESET_VECTOR; + _ID_SECTION = _ID_SECTION_END - SIZEOF(.id); - . = 0xffffffc0; + . = _FIT_POINTER; .fit_pointer (.): { KEEP(*(.fit_pointer)); } + _FIT_POINTER = SIZEOF(.fit_pointer) ? 0xffffffc0 : _X86_RESET_VECTOR; . = 0xfffffff0; + _X86_RESET_VECTOR = .; .reset . : { *(.reset); . = 15; -- To view, visit https://review.coreboot.org/c/coreboot/+/48499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d3a58c82efd3bbf94f4bc80ec5bbc97d5b1c109 Gerrit-Change-Number: 48499 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: security/intel/txt/ramstage.c: Fix clearing secrets on CBNT
by Arthur Heymans (Code Review) 05 Jan '21

05 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47934 ) Change subject: security/intel/txt/ramstage.c: Fix clearing secrets on CBNT ...................................................................... security/intel/txt/ramstage.c: Fix clearing secrets on CBNT With CBNT it looks like only the the TXT_E2STS_SECRET_STS should be looked at. Change-Id: Iff4436501b84f5c209add845b3cd3a62782d17e6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/txt/ramstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47934/1 diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 80bf3f9..4e38d32 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -90,7 +90,7 @@ return; /* Check for fatal ACM error and TXT reset */ - if (get_wake_error_status()) { +// if (get_wake_error_status()) { /* * Check if secrets bit needs to be reset. Only platforms that support * CONFIG(PLATFORM_HAS_DRAM_CLEAR) will be able to run this code. @@ -106,7 +106,7 @@ intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); die("Waiting for platform reset...\n"); } - } +// } } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, check_secrets_txt, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/47934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff4436501b84f5c209add845b3cd3a62782d17e6 Gerrit-Change-Number: 47934 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: util: Make sure all util dirs have description files at top level
by Martin Roth (Code Review) 05 Jan '21

05 Jan '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48961 ) Change subject: util: Make sure all util dirs have description files at top level ...................................................................... util: Make sure all util dirs have description files at top level New util directories have been added with no description.md file. The description file for supermicro was added at a secondary level, which doesn't help a user find the util since no path was added. Move it up to the top level. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I40b4c25dd7706513e96c6b8078a34160f8bb901e --- A util/apcb/description.md A util/mainboard/description.md A util/qemu/description.md A util/spd_tools/description.md A util/supermicro/description.md D util/supermicro/smcbiosinfo/description.md 6 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/48961/1 diff --git a/util/apcb/description.md b/util/apcb/description.md new file mode 100644 index 0000000..674243a --- /dev/null +++ b/util/apcb/description.md @@ -0,0 +1,4 @@ +AMD PSP Control Block tools + +* _apcb_edit.py_ - This tool allows patching an existing APCB binary with + specific SPDs and GPIO selection pins. `Python3` diff --git a/util/mainboard/description.md b/util/mainboard/description.md new file mode 100644 index 0000000..4050a80 --- /dev/null +++ b/util/mainboard/description.md @@ -0,0 +1,3 @@ +mainboard specific scripts + +* _google_ - Directory for google mainboard specific scripts diff --git a/util/qemu/description.md b/util/qemu/description.md new file mode 100644 index 0000000..6e3a16c --- /dev/null +++ b/util/qemu/description.md @@ -0,0 +1,3 @@ +__qemu__ + +- Makefile & comprehensive default config for QEMU Q35 emulation diff --git a/util/spd_tools/description.md b/util/spd_tools/description.md new file mode 100644 index 0000000..aa12781 --- /dev/null +++ b/util/spd_tools/description.md @@ -0,0 +1,11 @@ +Tools for generating SPD files for DDR4 memory used in platforms with +memory down configuration. + + + +* _gen_spd.go_ - Generates de-duplicated SPD files using a + global memory part list provided by the + mainboard in JSON format. `Go` + +* _gen_part_id.go_ - Allocates DRAM strap IDs for different + DDR4 memory parts used by the board. `Go` diff --git a/util/supermicro/description.md b/util/supermicro/description.md new file mode 100644 index 0000000..8584016 --- /dev/null +++ b/util/supermicro/description.md @@ -0,0 +1,3 @@ +Tools for supermicro platforms + +* _smcbiosinfo_ - Generates SMC biosinfo for BMC BIOS updates `C` diff --git a/util/supermicro/smcbiosinfo/description.md b/util/supermicro/smcbiosinfo/description.md deleted file mode 100644 index 21170eb..0000000 --- a/util/supermicro/smcbiosinfo/description.md +++ /dev/null @@ -1 +0,0 @@ -Generates SMC biosinfo for BMC BIOS updates `C` -- To view, visit https://review.coreboot.org/c/coreboot/+/48961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b4c25dd7706513e96c6b8078a34160f8bb901e Gerrit-Change-Number: 48961 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/sandybridge: Replace memset with initializer
by Angel Pons (Code Review) 05 Jan '21

05 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49064 ) Change subject: nb/intel/sandybridge: Replace memset with initializer ...................................................................... nb/intel/sandybridge: Replace memset with initializer There's no need to use `memset` here. Change-Id: I0478bc3ff25b75bf0b554aa83ead6a63fcbd975c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/49064/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3c60a9f..61663b8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1137,11 +1137,9 @@ static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int rcven_delta; - int statistics[NUM_LANES][51]; + int statistics[NUM_LANES][51] = {0}; int lane, i; - memset(statistics, 0, sizeof(statistics)); - for (rcven_delta = -25; rcven_delta <= 25; rcven_delta++) { FOR_ALL_LANES { -- To view, visit https://review.coreboot.org/c/coreboot/+/49064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0478bc3ff25b75bf0b554aa83ead6a63fcbd975c Gerrit-Change-Number: 49064 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/google/zork: mb/google/zork: update DRAM table for morphius
by Kevin Chiu (Code Review) 05 Jan '21

05 Jan '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48723 ) Change subject: mb/google/zork: mb/google/zork: update DRAM table for morphius ...................................................................... mb/google/zork: mb/google/zork: update DRAM table for morphius Add Hynix DDR4 DRAM, index was generated by gen_part_id H5ANAG6NCJR-XNC BUG=b:175911098 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I853a316c266afafeecff67b263005a77be316e2b Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/morphius/spd/Makefile.inc M src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/48723/1 diff --git a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc index 2eb864d..6ec9ecb 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc @@ -3,7 +3,7 @@ SPD_SOURCES = SPD_SOURCES += ddr4-spd-7.hex # ID = 0(0b0000) Parts = K4AAG165WA-BCWE -SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-9.hex # ID = 1(0b0001) Parts = H5ANAG6NCJR-XNC SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE diff --git a/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt index 7210071..0ba45c5 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt @@ -8,3 +8,4 @@ K4AAG165WA-BCWE 7 (0111) H5ANAG6NCMR-XNC 8 (1000) K4A8G165WC-BCWE 9 (1001) +H5ANAG6NCJR-XNC 1 (0001) diff --git a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt index 3297639..c4cd034 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt @@ -16,3 +16,4 @@ K4AAG165WA-BCWE, 7 H5ANAG6NCMR-XNC, 8 K4A8G165WC-BCWE, 9 +H5ANAG6NCJR-XNC -- To view, visit https://review.coreboot.org/c/coreboot/+/48723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I853a316c266afafeecff67b263005a77be316e2b Gerrit-Change-Number: 48723 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: mb/clevo/l140cu: Move FSP-M config hook to mainboard level
by Felix Singer (Code Review) 04 Jan '21

04 Jan '21

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49077 to look at the new patch set (#4). Change subject: mb/clevo/l140cu: Move FSP-M config hook to mainboard level ...................................................................... mb/clevo/l140cu: Move FSP-M config hook to mainboard level Every variant needs to configure memory init parameters. Thus, move the hook for the FSP-M configuration to mainboard level being able to do common configurations there. Also, include the variants romstage.c on mainboard level instead of variant level. Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Makefile.inc A src/mainboard/clevo/cml-u/include/variant/romstage.h A src/mainboard/clevo/cml-u/romstage.c M src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c 5 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/49077/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656 Gerrit-Change-Number: 49077 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/clevo/l140cu: Move FSP-M config hook to mainboard level
by Felix Singer (Code Review) 04 Jan '21

04 Jan '21

Hello Patrick Georgi, Martin Roth, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49077 to look at the new patch set (#3). Change subject: mb/clevo/l140cu: Move FSP-M config hook to mainboard level ...................................................................... mb/clevo/l140cu: Move FSP-M config hook to mainboard level Every variant needs to configure memory init parameters. Thus, move the hook for the FSP-M configuration to mainboard level being able to do common configurations there. Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Makefile.inc A src/mainboard/clevo/cml-u/include/variant/romstage.h A src/mainboard/clevo/cml-u/romstage.c M src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc M src/mainboard/clevo/cml-u/variants/l140cu/romstage.c 5 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/49077/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656 Gerrit-Change-Number: 49077 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/apl,mb/*: move LPC/eSPI pad configuration to boards
by Shaunak Saha (Code Review) 04 Jan '21

04 Jan '21

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48799 ) Change subject: soc/intel/apl,mb/*: move LPC/eSPI pad configuration to boards ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61717d9ddc57b174c6a2e31f950c22ad0b276f5d Gerrit-Change-Number: 48799 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Jan 2021 20:17:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2021