coreboot-gerrit January 2021

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Change in coreboot[master]: mb/kontron/mal10: Move include directories to mb level
by Felix Singer (Code Review) 05 Jan '21

05 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48142 ) Change subject: mb/kontron/mal10: Move include directories to mb level ...................................................................... mb/kontron/mal10: Move include directories to mb level Move include directories from carriers and variants to mainboard level so that the headers can be reused. Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I55af05cb84b97d567ce1fc3b6151c34d1eda183f --- M src/mainboard/kontron/mal10/Makefile.inc R src/mainboard/kontron/mal10/include/carrier/gpio.h R src/mainboard/kontron/mal10/include/variant/gpio.h 3 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/48142/1 diff --git a/src/mainboard/kontron/mal10/Makefile.inc b/src/mainboard/kontron/mal10/Makefile.inc index 885786f..7fbab00 100644 --- a/src/mainboard/kontron/mal10/Makefile.inc +++ b/src/mainboard/kontron/mal10/Makefile.inc @@ -3,7 +3,5 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include - subdirs-y += carriers/$(CARRIER_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/carriers/$(CARRIER_DIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h b/src/mainboard/kontron/mal10/include/carrier/gpio.h similarity index 100% rename from src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h rename to src/mainboard/kontron/mal10/include/carrier/gpio.h diff --git a/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h b/src/mainboard/kontron/mal10/include/variant/gpio.h similarity index 100% rename from src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h rename to src/mainboard/kontron/mal10/include/variant/gpio.h -- To view, visit https://review.coreboot.org/c/coreboot/+/48142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55af05cb84b97d567ce1fc3b6151c34d1eda183f Gerrit-Change-Number: 48142 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/purism/librem_cnl: Fix HDA verb NID count for Librem Mini
by Matt DeVillier (Code Review) 05 Jan '21

05 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49106 ) Change subject: mb/purism/librem_cnl: Fix HDA verb NID count for Librem Mini ...................................................................... mb/purism/librem_cnl: Fix HDA verb NID count for Librem Mini Fix off-by-1 count of NID entries. Change-Id: I65f70d084022c99233144b460542a793eae2acf3 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/49106/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c index c3daf3c..5f410b2 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c @@ -5,7 +5,7 @@ const u32 cim_verb_data[] = { 0x10ec0269, /* Codec Vendor/Device ID: Realtek ALC293 */ 0x10ec0000, /* Subsystem ID */ - 11, /* Number of entries */ + 10, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x10ec0000), AZALIA_PIN_CFG(0, 0x12, 0x40000000), -- To view, visit https://review.coreboot.org/c/coreboot/+/49106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f70d084022c99233144b460542a793eae2acf3 Gerrit-Change-Number: 49106 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: ACPI: Final APM_CNT_GNVS_UPDATE cleanup
by Kyösti Mälkki (Code Review) 05 Jan '21

05 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48699 ) Change subject: ACPI: Final APM_CNT_GNVS_UPDATE cleanup ...................................................................... ACPI: Final APM_CNT_GNVS_UPDATE cleanup All platforms moved to initialise GNVS at the time of SMM module loading. Change-Id: I31b5652a946b0d9bd1909ff8bde53b43e06e2cd9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/acpi_s3.c M src/cpu/x86/smm/smi_trigger.c M src/include/cpu/x86/smm.h 3 files changed, 1 insertion(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/48699/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 43a68f9..ec1fafc 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -5,7 +5,6 @@ #include <acpi/acpi.h> #include <arch/cpu.h> #include <commonlib/helpers.h> -#include <cpu/x86/smm.h> #include <fallback.h> #include <timestamp.h> @@ -18,9 +17,6 @@ void __noreturn acpi_resume(void *wake_vec) { - /* Restore GNVS pointer in SMM if found. */ - apm_control(APM_CNT_GNVS_UPDATE); - /* Call mainboard resume handler first, if defined. */ mainboard_suspend_resume(); diff --git a/src/cpu/x86/smm/smi_trigger.c b/src/cpu/x86/smm/smi_trigger.c index 4b63745..7e3ddb1 100644 --- a/src/cpu/x86/smm/smi_trigger.c +++ b/src/cpu/x86/smm/smi_trigger.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi_gnvs.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -static void set_smm_gnvs_ptr(void); - int apm_control(u8 cmd) { if (!CONFIG(HAVE_SMI_HANDLER)) @@ -23,9 +20,6 @@ case APM_CNT_ACPI_ENABLE: printk(BIOS_DEBUG, "Enabling ACPI via APMC.\n"); break; - case APM_CNT_GNVS_UPDATE: - set_smm_gnvs_ptr(); - return 0; case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "Finalizing SMM.\n"); break; @@ -45,32 +39,3 @@ printk(BIOS_DEBUG, "APMC done.\n"); return 0; } - -static void set_smm_gnvs_ptr(void) -{ - uintptr_t gnvs_address; - - if (CONFIG(ACPI_NO_SMI_GNVS)) { - printk(BIOS_WARNING, "%s() is not implemented\n", __func__); - return; - } - - gnvs_address = (uintptr_t)acpi_get_gnvs(); - if (!gnvs_address) - return; - - /* - * Issue SMI to set the gnvs pointer in SMM. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" (gnvs_address), - "d" (APM_CNT) - ); -} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 6dfe08d..9106842 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -22,11 +22,10 @@ #define APM_CNT_PST_CONTROL 0x80 #define APM_CNT_ACPI_DISABLE 0x1e #define APM_CNT_ACPI_ENABLE 0xe1 -#define APM_CNT_MBI_UPDATE 0xeb -#define APM_CNT_GNVS_UPDATE 0xea #define APM_CNT_ROUTE_ALL_XHCI 0xca #define APM_CNT_FINALIZE 0xcb #define APM_CNT_LEGACY 0xcc +#define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_SMMINFO 0xec #define APM_CNT_SMMSTORE 0xed #define APM_CNT_ELOG_GSMI 0xef -- To view, visit https://review.coreboot.org/c/coreboot/+/48699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31b5652a946b0d9bd1909ff8bde53b43e06e2cd9 Gerrit-Change-Number: 48699 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: arch/x86: Pass GNVS as parameter to SMM module
by Kyösti Mälkki (Code Review) 05 Jan '21

05 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48698 ) Change subject: arch/x86: Pass GNVS as parameter to SMM module ...................................................................... arch/x86: Pass GNVS as parameter to SMM module Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/smm_module_handler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 27 files changed, 4 insertions(+), 210 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/48698/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3ba5684..8532d59 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -134,8 +134,10 @@ /* Make sure to set the global runtime. It's OK to race as the value * will be the same across CPUs as well as multiple SMIs. */ - if (smm_runtime == NULL) + if (smm_runtime == NULL) { smm_runtime = runtime; + gnvs = (void *)(uintptr_t)smm_runtime->gnvs_ptr; + } if (cpu >= CONFIG_MAX_CPUS) { console_init(); diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 1810821..6fedba7 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -18,8 +18,6 @@ #include <soc/pm.h> #include <soc/nvs.h> -static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -282,7 +280,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -312,23 +309,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 967a710..2df6410 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -497,8 +497,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index fd5ffce..9577536 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -396,9 +396,6 @@ else gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - /* Add it to DSDT */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 6e250d8..a4fdb01 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -18,8 +18,6 @@ #include <soc/gpio.h> #include <smmstore.h> -static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -261,7 +259,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -291,23 +288,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 73b83e4..5a29b02 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -646,9 +646,6 @@ } } - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - /* Add it to DSDT. */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index fd5d452..5ed52d8 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -23,8 +23,6 @@ #include <drivers/intel/gma/i915_reg.h> #include <smmstore.h> -static u8 smm_initialized = 0; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -313,7 +311,6 @@ static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -333,24 +330,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index d2177294..69f7a59 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -232,8 +232,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index dc32970..51a3003 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -330,8 +330,6 @@ const struct smm_save_state_ops *save_state_ops) { uint8_t reg8; - void *state = NULL; - static int smm_initialized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -361,25 +359,6 @@ pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = find_save_state(save_state_ops, reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(save_state_ops); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index e7d29ff..2a847ed 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -258,8 +258,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index cae8b9b..ae15795 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -17,8 +17,6 @@ #include <soc/pm.h> #include <soc/nvs.h> -static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -221,7 +219,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -252,20 +249,6 @@ case APM_CNT_FINALIZE: finalize(); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) southbridge_smi_store(); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 0083be5..d654a58 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -552,8 +552,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 4c17eea..184eb6b 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -216,8 +216,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8af8065..4515261 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -659,8 +659,6 @@ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 40672f8..1a9e5b4 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -185,23 +185,6 @@ xhci_sleep(slp_type); } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; - if (smm_region_overlaps_handler(&r)) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index c175647..c9cf544 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -4,7 +4,6 @@ #define INTEL_COMMON_PMUTIL_H #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 @@ -129,10 +128,8 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); void pch_log_state(void); #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7610aa1..d59e29c 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -17,8 +17,6 @@ #include "pmutil.h" -static int smm_initialized = 0; - u16 get_pmbase(void) { return lpc_get_pmbase(); @@ -198,7 +196,7 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; int node; @@ -302,14 +300,6 @@ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - southbridge_update_gnvs(reg8, &smm_initialized); - break; case APM_CNT_FINALIZE: if (mainboard_finalized) { printk(BIOS_DEBUG, "SMI#: Already finalized\n"); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9ac8942..4db9351 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -491,8 +491,6 @@ acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index f1be5c2..03480a7 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -19,11 +19,6 @@ /* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 652da54..821a0b7 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -461,8 +461,6 @@ memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 537e544..046cc2b 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -14,10 +14,6 @@ struct global_nvs *gnvs; #endif -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 1f4cf29..ad9bac1 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -485,8 +485,6 @@ memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 7d79620..6a6c5b4 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -13,11 +13,6 @@ * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d2a3404..0895ddd 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -555,8 +555,6 @@ gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 0c5e954..e83a9de 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -147,22 +147,6 @@ #undef IOTRAP } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 915c181..586e626 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -712,8 +712,6 @@ /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9c68a54..bd44500 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -19,8 +19,6 @@ #include "pch.h" #include "nvs.h" -static u8 smm_initialized = 0; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -262,7 +260,6 @@ static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; static int chipset_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -304,24 +301,6 @@ enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ROUTE_ALL_XHCI: usb_xhci_route_all(); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/48698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Gerrit-Change-Number: 48698 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/google/hatch (baseboard): add ACPI backlight support
by Matt DeVillier (Code Review) 05 Jan '21

05 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49058 ) Change subject: mb/google/hatch (baseboard): add ACPI backlight support ...................................................................... mb/google/hatch (baseboard): add ACPI backlight support Add ACPI backlight support for boards selecting BOARD_GOOGLE_BASEBOARD_HATCH. PUFF-based variants do not have an attached display, so do not need this. Test: build/boot Windows 10 20H2 on google/akemi, verify display backlight controls functional. Change-Id: I5ce4c6e1c78299e89760a1356da452d56ba0aee6 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/variants/akemi/overridetree.cb M src/mainboard/google/hatch/variants/dratini/overridetree.cb M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/jinlon/overridetree.cb M src/mainboard/google/hatch/variants/kindred/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/hatch/variants/stryke/overridetree.cb 13 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/49058/1 diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 1395c8f..d668440 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -26,6 +26,9 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> +#if CONFIG(BOARD_GOOGLE_BASEBOARD_HATCH) + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> +#endif } } diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 8ae350c..97a6eaf 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -72,6 +72,9 @@ register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 3b094a3..3605196 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -69,6 +69,9 @@ register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index e13270f..01afa16 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -68,6 +68,9 @@ register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 4241a46..c935620 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -60,6 +60,9 @@ }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 6fbe950..129bb26 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -76,6 +76,9 @@ }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index 750e068..16402af 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -69,6 +69,9 @@ register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 02.0 on chip drivers/gfx/generic register "device_count" = "1" diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index c06f35b..f27423f 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -105,6 +105,9 @@ register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 740a7d8..266346b 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -73,6 +73,9 @@ }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 29b87e4..74b3e1f 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -88,6 +88,9 @@ register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index ff61d80..8805a32 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -121,6 +121,9 @@ register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index 8cdb2a9..b7f6ff2 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -57,6 +57,9 @@ }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb index 3611e58..aa73ab6 100644 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -58,6 +58,9 @@ register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/49058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce4c6e1c78299e89760a1356da452d56ba0aee6 Gerrit-Change-Number: 49058 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/google/reef (and variants): add ACPI backlight support
by Matt DeVillier (Code Review) 05 Jan '21

05 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49057 ) Change subject: mb/google/reef (and variants): add ACPI backlight support ...................................................................... mb/google/reef (and variants): add ACPI backlight support Enables backlight control under Windows 10. Test: build/boot Windows 10 20H2 on google/reef, verify display backlight controls functional. Change-Id: I4ce613badbdcfb9c843f52408df26c6cbb4b82a2 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/reef/dsdt.asl M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb 6 files changed, 16 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/49057/1 diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index f87b962..ecd44f6 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -25,6 +25,7 @@ #include <soc/intel/apollolake/acpi/northbridge.asl> #include <soc/intel/apollolake/acpi/southbridge.asl> #include <soc/intel/apollolake/acpi/pch_hda.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index a1b7a4c..9aadc9e 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -125,7 +125,9 @@ device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 6492931..e8f8cc3 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -125,7 +125,9 @@ device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 0dbaa29..af459be 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -134,7 +134,9 @@ device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index ba19369..91555ad 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -121,7 +121,9 @@ device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 3be68dd..d4e9705 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -130,7 +130,9 @@ device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC -- To view, visit https://review.coreboot.org/c/coreboot/+/49057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ce613badbdcfb9c843f52408df26c6cbb4b82a2 Gerrit-Change-Number: 49057 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros
by Maxim Polyakov (Code Review) 05 Jan '21

05 Jan '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43411 ) Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ...................................................................... mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*). $ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. [*] To do this, ignore some bit fields. See Patchset 1 | Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/1 diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index c266dde..f8f5b08 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -10,158 +10,158 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { - /* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), - /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), - /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), - /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), - /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), - /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), - /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x84000102, 0x0), - /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x0), - /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), - /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x40100102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x04000201, 0x0), - /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), - /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), - /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), - /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x0), - /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), - /* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, 0x44000702, 0x0), - /* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, 0x44000702, 0x0), - /* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, 0x44000702, 0x0), - /* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x40100102, 0x0), - /* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), - /* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), - /* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), - /* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), - /* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), - /* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), - /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), - /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), - /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), - /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x80880102, 0x3000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), - /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), - /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), - /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), - /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), - /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), - /* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0), - /* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x40900100, 0x1000), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), - /* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x0), - /* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), - /* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), - /* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), - /* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), - /* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), - /* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), - /* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), - /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), - /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), - /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), - /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), - /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), - /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), - /* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), - /* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), - /* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), - /* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), - /* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), - /* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), - /* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), - /* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), - /* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), - /* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), - /* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000100, 0x0), - /* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, 0x44000700, 0x0), - /* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x0), - /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), - /* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), - /* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), - /* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), - /* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), - /* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), - /* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), - /* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), - /* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x42880100, 0x0), - /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), - /* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), - /* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, 0x04000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x82880102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0), - /* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), - /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000702, 0x0), - /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), - /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), - /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), - /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), - /* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), - /* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x40900100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x84000200, 0x1000), - /* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), - /* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), - /* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), - /* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), - /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), - /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), - /* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), - /* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), - /* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), - /* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), - /* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), - /* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), - /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F13, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0), - /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), - /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), - /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), - /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), - /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), - /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), - /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), - /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), - /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), - /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), - /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), - /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), - /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0), - /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), +/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_A12, 1, PWROK), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPIO */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_B15, 0, DEEP), +/* GPIO */ PAD_NC(GPP_B16, NONE), +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), +/* GPIO */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), +/* RESERVED - GPP_C6 */ +/* RESERVED - GPP_C7 */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), +/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), +/* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP), +/* GPIO */ PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, IOAPIC, SCI), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_E9, 0, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), +/* GPIO */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Gerrit-Change-Number: 43411 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: MAINTAINERS: Add maintainer for ACPI
by Patrick Georgi (Code Review) 05 Jan '21

05 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48970 ) Change subject: MAINTAINERS: Add maintainer for ACPI ...................................................................... MAINTAINERS: Add maintainer for ACPI Change-Id: I65fdee350273c58e027a002dba1f97a56115e195 Signed-off-by: Lance Zhao <lance.zhao(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48970 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M MAINTAINERS 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Bora Guvendik: Looks good to me, approved Felix Singer: Looks good to me, but someone else must approve Maxim Polyakov: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index 49fbc38..7a82159 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,8 @@ F: src/drivers/aspeed/ast2050/ ACPI +M: Lance Zhao <lance.zhao(a)gmail.com> +S: Supported F: src/acpi/ F: src/arch/x86/acpi/ F: util/acpi/ -- To view, visit https://review.coreboot.org/c/coreboot/+/48970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65fdee350273c58e027a002dba1f97a56115e195 Gerrit-Change-Number: 48970 Gerrit-PatchSet: 5 Gerrit-Owner: Lance Zhao Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/vpd: Add support to read device serial from VPD
by Matt DeVillier (Code Review) 05 Jan '21

05 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49050 ) Change subject: drivers/vpd: Add support to read device serial from VPD ...................................................................... drivers/vpd: Add support to read device serial from VPD Add functions to read the system and mainboard serial numbers from VPD tables stored in flash. Test: build/boot google/akemi with RO_VPD region persisted from stock Google firmware, verify system/mainboard serial numbers present via dmidecode. Change-Id: I14ae07cd8b764e1e22d58577c7cc697ca1496bd5 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/vpd/Kconfig M src/drivers/vpd/vpd.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/49050/1 diff --git a/src/drivers/vpd/Kconfig b/src/drivers/vpd/Kconfig index 0b16058..6bfbf4f 100644 --- a/src/drivers/vpd/Kconfig +++ b/src/drivers/vpd/Kconfig @@ -19,3 +19,8 @@ default 0x4000 help Size in bytes of the FMAP region created to store VPD tables. + +config SMBIOS_SERIAL_FROM_VPD + bool "Load device serial from VPD" + depends on VPD && GENERATE_SMBIOS_TABLES + default y diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index d3ff370..14dad8a 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -6,6 +6,7 @@ #include <ctype.h> #include <fmap.h> #include <program_loading.h> +#include <smbios.h> #include <string.h> #include <timestamp.h> #include <types.h> @@ -297,4 +298,26 @@ return true; } +#if CONFIG(SMBIOS_SERIAL_FROM_VPD) +#define VPD_KEY_SYSTEM_SERIAL "serial_number" +#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" +#define VPD_SERIAL_LEN 64 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +const char *smbios_mainboard_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} +#endif + ROMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) -- To view, visit https://review.coreboot.org/c/coreboot/+/49050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14ae07cd8b764e1e22d58577c7cc697ca1496bd5 Gerrit-Change-Number: 49050 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 22

Change in coreboot[master]: drivers/vpd: Add VPD region to default FMAP when selected
by Matt DeVillier (Code Review) 05 Jan '21

05 Jan '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49049 ) Change subject: drivers/vpd: Add VPD region to default FMAP when selected ...................................................................... drivers/vpd: Add VPD region to default FMAP when selected Currently, use of the VPD driver to read VPD tables from flash requires the use of a custom FMAP with one or more VPD regions. Extend this funtionality to boards using the default FMAP by creating a dedicated VPD region when the driver is selected. Test: build qemu target with CONFIG_VPD selected, verify entry added to build/fmap.fmd. Change-Id: Ie9e3c7cf11a6337a43223a6037632a4d9c84d988 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M Makefile.inc M src/drivers/vpd/Kconfig M util/cbfstool/default-x86.fmd 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/49049/1 diff --git a/Makefile.inc b/Makefile.inc index bacddf2..ae61c2e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -983,6 +983,15 @@ FMAP_SPD_CACHE_ENTRY := endif +ifeq ($(CONFIG_VPD),y) +FMAP_VPD_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000) +FMAP_VPD_SIZE := $(CONFIG_VPD_FMAP_SIZE) +FMAP_VPD_ENTRY := $(CONFIG_VPD_FMAP_NAME)@$(FMAP_VPD_BASE) $(FMAP_VPD_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_VPD_BASE) $(FMAP_VPD_SIZE)) +else +FMAP_VPD_ENTRY := +endif + # # X86 FMAP region # @@ -1060,6 +1069,7 @@ -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \ + -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp diff --git a/src/drivers/vpd/Kconfig b/src/drivers/vpd/Kconfig index eda9130..0b16058 100644 --- a/src/drivers/vpd/Kconfig +++ b/src/drivers/vpd/Kconfig @@ -5,3 +5,17 @@ default n help Enable support for flash based vital product data. + +config VPD_FMAP_NAME + string + depends on VPD + default "RO_VPD" + help + Name of the FMAP region created in the default FMAP to store VPD tables. + +config VPD_FMAP_SIZE + hex + depends on VPD + default 0x4000 + help + Size in bytes of the FMAP region created to store VPD tables. diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 25c5096..41be782 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -13,6 +13,7 @@ ##MRC_CACHE_ENTRY## ##SMMSTORE_ENTRY## ##SPD_CACHE_ENTRY## + ##VPD_ENTRY## FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } -- To view, visit https://review.coreboot.org/c/coreboot/+/49049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9e3c7cf11a6337a43223a6037632a4d9c84d988 Gerrit-Change-Number: 49049 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 6

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