coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Benjamin Doron (Code Review) 05 Jan '21

05 Jan '21

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Jan 2021 19:50:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{common,adl}: drop unneeded Kconfig PMC_LOW_POWER_MODE_PROGRAM
by Michael Niewöhner (Code Review) 05 Jan '21

05 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49125 ) Change subject: soc/intel/{common,adl}: drop unneeded Kconfig PMC_LOW_POWER_MODE_PROGRAM ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/49125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1ffb0ee0078e923fbaeaca640d215408b8f4ec8 Gerrit-Change-Number: 49125 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Jan 2021 19:38:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: drop duplicate PM ACPI timer ...
by Michael Niewöhner (Code Review) 05 Jan '21

05 Jan '21

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45958 to look at the new patch set (#39). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: drop duplicate PM ACPI timer disabling ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,ehl}: drop duplicate PM ACPI timer disabling FSP already disables the PM ACPI timer, when EnableTcoTimer=0, so there is no need to do it again in coreboot. Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 12 files changed, 3 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45958/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/45958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Gerrit-Change-Number: 45958 Gerrit-PatchSet: 39 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state f...
by Michael Niewöhner (Code Review) 05 Jan '21

05 Jan '21

Hello Lance Zhao, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Sridhar Siricilla, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45957 to look at the new patch set (#39). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state from Kconfig ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state from Kconfig Set the FSP option for PM ACPI timer enablement from the Kconfig option to be able to disable the timer for power savings. Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/finalize.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/fsp_params.c 11 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45957/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/45957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Gerrit-Change-Number: 45957 Gerrit-PatchSet: 39 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/acer/aspire_vn7_572g: Optimus support
by Benjamin Doron (Code Review) 05 Jan '21

05 Jan '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40628 to look at the new patch set (#10). Change subject: mb/acer/aspire_vn7_572g: Optimus support ...................................................................... mb/acer/aspire_vn7_572g: Optimus support Add Nvidia Optimus support to this board. Values were obtained from the schematics, the Switchable Graphics ACPI table and OpRegion and then confirmed by reverse engineering SwitchableGraphicsPei. This patch has additional dependencies on CB:28380 and CB:40625. Tested, working. Any bugs are likely in the Optimus or PEG ACPI code. Change-Id: Iac971137ff6805628eb219adedee0c55fb8caef9 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/acpi/optimus_mb.asl M src/mainboard/acer/aspire_vn7_572g/dsdt.asl 3 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/40628/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/40628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac971137ff6805628eb219adedee0c55fb8caef9 Gerrit-Change-Number: 40628 Gerrit-PatchSet: 10 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/acer/aspire_vn7_572g: Optimus support
by Benjamin Doron (Code Review) 05 Jan '21

05 Jan '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40628 to look at the new patch set (#8). Change subject: mb/acer/aspire_vn7_572g: Optimus support ...................................................................... mb/acer/aspire_vn7_572g: Optimus support Add Nvidia Optimus support to this board. Values were obtained from the schematics, the Switchable Graphics ACPI table and OpRegion and then confirmed by reverse engineering SwitchableGraphicsPei. This patch has additional dependencies on CB:28380 and CB:40625. Tested, working. Any bugs are likely in the Optimus or PEG ACPI code. Change-Id: Iac971137ff6805628eb219adedee0c55fb8caef9 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- A src/mainboard/acer/aspire_vn7_572g/acpi/optimus_mb.asl 1 file changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/40628/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/40628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac971137ff6805628eb219adedee0c55fb8caef9 Gerrit-Change-Number: 40628 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Benjamin Doron (Code Review) 05 Jan '21

05 Jan '21

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40625 to look at the new patch set (#14). Change subject: [WIP] skl: PEG for Optimus ...................................................................... [WIP] skl: PEG for Optimus Creates PEG ACPI device for Optimus. Tested, nouveau driver works on an Acer Aspire VN7-572G (Skylake-U) and `DRI_PRIME=1 glxinfo` reports the dGPU as renderer. Bugs (need to confirm): - "Data Link Layer Link Active not set in 1000ms" TODO: Test NVIDIA binary driver Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- A src/soc/intel/skylake/acpi/peg.asl 1 file changed, 254 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40625/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 14 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Benjamin Doron (Code Review) 05 Jan '21

05 Jan '21

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40625 to look at the new patch set (#13). Change subject: [WIP] skl: PEG for Optimus ...................................................................... [WIP] skl: PEG for Optimus Creates PEG ACPI device for Optimus. Bugs: - "Data Link Layer Link Active not set in 1000ms" Tested, nouveau driver works on an Acer Aspire VN7-572G (Skylake-U) and `DRI_PRIME=1 glxinfo` reports the dGPU as renderer. Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- A src/soc/intel/skylake/acpi/peg.asl 1 file changed, 254 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40625/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 13 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Angel Pons (Code Review) 05 Jan '21

05 Jan '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… PS2, Line 550: 1 What happens if setting this to zero? -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 05 Jan 2021 18:49:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Felix Singer (Code Review) 05 Jan '21

05 Jan '21

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… PS2, Line 554: !dev->subsystem_vendor || !dev->subsystem_device if (dev && (...)). Same below. https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… PS2, Line 552: /* Program XHCI SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } : : /* Program HDAudio SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } Why is this needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 05 Jan 2021 18:29:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2021