coreboot-gerrit January 2021

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Change in coreboot[master]: mb/google/volteer/var/voema: Enable IPU for voema
by David Wu (Code Review) 05 Jan '21

05 Jan '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49002 ) Change subject: mb/google/volteer/var/voema: Enable IPU for voema ...................................................................... mb/google/volteer/var/voema: Enable IPU for voema Enable IPU for voema for MIPI camera. BUG=169551066 TEST=IPU is enabled and shows in lspci. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I34736bffd4dc61a840003afe5afd6a9c8dc32e62 --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/49002/1 diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index f612beb..daea432 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -17,6 +17,7 @@ register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" device domain 0 on + device ref ipu on end # IPU device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/49002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34736bffd4dc61a840003afe5afd6a9c8dc32e62 Gerrit-Change-Number: 49002 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
by Benjamin Doron (Code Review) 05 Jan '21

05 Jan '21

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45002 ) Change subject: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size ...................................................................... Patch Set 5: (4 comments) https://review.coreboot.org/c/coreboot/+/45002/4/src/soc/intel/cannonlake/s… File src/soc/intel/cannonlake/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/45002/4/src/soc/intel/cannonlake/s… PS4, Line 21: > probably commonlib/helpers. […] It compiled locally (HOSTGCC). But I do see that its used. https://review.coreboot.org/c/coreboot/+/45002/4/src/soc/intel/cannonlake/s… PS4, Line 157: _WARNING, : "TSEG base not al > fits in one line Done https://review.coreboot.org/c/coreboot/+/45002/4/src/soc/intel/skylake/smmr… File src/soc/intel/skylake/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/45002/4/src/soc/intel/skylake/smmr… PS4, Line 21: > probably commonlib/helpers. […] Done https://review.coreboot.org/c/coreboot/+/45002/4/src/soc/intel/skylake/smmr… PS4, Line 157: _WARNING, : "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); > fits in one line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Gerrit-Change-Number: 45002 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 17:59:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
by Benjamin Doron (Code Review) 05 Jan '21

05 Jan '21

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45002 to look at the new patch set (#5). Change subject: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size ...................................................................... soc/intel/{cnl,skl}: Add alignment check for TSEG base and size Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG base and size) to remaining SoCs. Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/skylake/smmrelocate.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45002/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Gerrit-Change-Number: 45002 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/l140cu: Add vboot support
by Michael Niewöhner (Code Review) 05 Jan '21

05 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46602 ) Change subject: mb/clevo/l140cu: Add vboot support ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/fmds/vboot-roab.fmd: https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… PS5, Line 22: RW_VPD(PRESERVE) 0x2000 result of discussion on IRQ with Tim and Matt: don't add the VPD region if we don't have concrete plans to use it. even google tries not to use it that much because it's apparently a lot of trouble for ODMs -- To view, visit https://review.coreboot.org/c/coreboot/+/46602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb5e93eb55ece5b0e0d91b1a374d33e259c65cac Gerrit-Change-Number: 46602 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 17:42:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 05 Jan '21

05 Jan '21

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 05 Jan 2021 17:26:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Angel Pons (Code Review) 05 Jan '21

05 Jan '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 5: (10 comments) https://review.coreboot.org/c/coreboot/+/47892/5/Documentation/mainboard/sy… File Documentation/mainboard/system76/oryp5.md: https://review.coreboot.org/c/coreboot/+/47892/5/Documentation/mainboard/sy… PS5, Line 12: - eDP 16.1" or 17.3" 1920x1080 @ 144 Hz LCD Does backlight control work properly? I'd suggest testing under Windows. Some panel settings seem to be missing, which have been added recently in CB:48749 https://review.coreboot.org/c/coreboot/+/47892/5/Documentation/mainboard/sy… PS5, Line 15: 2666 MHz DDR4-2666 runs at 1333 MHz, or 2666 MT/s. https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/Kconfig: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 12: HAVE_SMI_HANDLER Isn't this selected elsewhere? https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 26: register "SaGv" = "SaGv_Enabled" > What's Halo? Is there a way I can verify that? Halo is the name of high-performance BGA CPUs. That is, the models ending in H, such as i7-9750H. Enabling SaGv makes FSP-M train the memory at two different speeds, which then allows dynamically changing the memory frequency in order to save power. However, memory training takes a long time (15 seconds, or even more), twice as much when SaGv is enabled. I don't know of a way to verify if SaGv is being used, though you could check if disabling SaGv or setting it to FixedHigh has an impact on battery life. You should also see that booting after reflashing or changing the DIMMs is about twice as fast, which can save lots of time when testing. https://review.coreboot.org/c/coreboot/+/47892/3/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/47892/3/src/mainboard/system76/ory… PS3, Line 87: subsystemid 0x1558 0x95e6 inherit > FSP integration guide only lists the registers with abbreviated names. […] Ah, cursed FSP https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 41: WARNING: must then be mapped from FSP value to PCH value Did you (or whoever originally wrote this) mean `from PCH value to FSP value`? https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/gpio.c: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 98: PAD_NC(GPP_C20, UP_20K), // UART2_RXD (test point) : PAD_NC(GPP_C21, UP_20K), // UART2_TXD (test point) This conflicts with the devicetree setting https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/hda_verb.c: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 25: // Enable DMIC microphone on ALC1220 : 0x02050036, : 0x02042a6a, > Jeremy got these magic numbers from the Windows driver, and putting them here happens to make the DM […] I guess people put these here because the cim_verb_data format only allows groups of 4 DWORDs. Ugh, I don't like it but can't come up with a simple solution... https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/romstage.c: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 52: DRAM > It seems all of these are copied from the header (error including). […] Thanks https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/romstage.c: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 25: 0 Shouldn't this be synchronized with ONBOARD_VGA_IS_PRIMARY in SoC code? -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 17:06:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/car: Remove runtime stack alignment enforcing
by Arthur Heymans (Code Review) 05 Jan '21

05 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37368 ) Change subject: arch/x86/car: Remove runtime stack alignment enforcing ...................................................................... arch/x86/car: Remove runtime stack alignment enforcing This is now checked at buildtime. Change-Id: Ice687b1a4de53de4799e90238c98cfef19a81136 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 6 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37368/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 73618d9..be96633 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -173,7 +173,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ - andl $0xfffffff0, %esp subl $4, %esp /* push TSC and BIST to stack */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..6c78ddb 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -219,7 +219,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ - andl $0xfffffff0, %esp subl $4, %esp /* push TSC and BIST to stack */ diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 5262b18..8c3009a 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -161,7 +161,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ - andl $0xfffffff0, %esp subl $4, %esp /* push TSC and BIST to stack */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fdeb0af..8fd240d 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -372,7 +372,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ - andl $0xfffffff0, %esp subl $4, %esp /* push TSC and BIST to stack */ diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 1fa0018..c1fe52d 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -37,8 +37,6 @@ movl $_ecar_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ - and $0xfffffff0, %esp - /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) movd %mm1, %rdi diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 0992d85..5d7eafa 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -174,7 +174,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the two pushes below. */ - andl $0xfffffff0, %esp sub $8, %esp /* push TSC value to stack */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice687b1a4de53de4799e90238c98cfef19a81136 Gerrit-Change-Number: 37368 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned
by Arthur Heymans (Code Review) 05 Jan '21

05 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37367 ) Change subject: arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned ...................................................................... arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned This can be used to avoid aligning the stack at runtime. Change-Id: I3aa068d947b6b6110fd7d002522f28a13e725cf7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37367/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 483a908..2d1723e 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -124,3 +124,4 @@ #if !CONFIG(ROMCC_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif +_bogus4 = ASSERT(_ecar_stack == ((_ecar_stack + 0xf) & ~0xf), "_ecar_stack must be 16 aligned"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa068d947b6b6110fd7d002522f28a13e725cf7 Gerrit-Change-Number: 37367 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{icl,tgl,jsl,ehl}: add LPIT support
by Michael Niewöhner (Code Review) 05 Jan '21

05 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49048 ) Change subject: soc/intel/{icl,tgl,jsl,ehl}: add LPIT support ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 5: > > > > > Patch Set 5: Code-Review+1 > > > > > > I didn't check JSL and EHL, but 0x193C is right on all other silicon > > > > EHL platform sample code / refcode uses it, no idea about JSL, though > > From 618876 yes that's still 0x193C ty for verifying! -- To view, visit https://review.coreboot.org/c/coreboot/+/49048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4 Gerrit-Change-Number: 49048 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Jan 2021 14:36:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state f...
by Michael Niewöhner (Code Review) 05 Jan '21

05 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45957 ) Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state from Kconfig ...................................................................... Patch Set 38: > Patch Set 38: > > Then why not skip ADL if the option is not there any more? hm? yeah, that's what I meant with "ack, will update later this day" :) -- To view, visit https://review.coreboot.org/c/coreboot/+/45957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Gerrit-Change-Number: 45957 Gerrit-PatchSet: 38 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 14:33:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2021