coreboot-gerrit January 2021

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Change in coreboot[master]: nb/intel/haswell/memmap.h: Clean up
by Angel Pons (Code Review) 05 Jan '21

05 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46993 ) Change subject: nb/intel/haswell/memmap.h: Clean up ...................................................................... nb/intel/haswell/memmap.h: Clean up Drop unused definition and remove outdated comments. Change-Id: I16033b558fe4c01a9394382dc0c9d0bdc66193d9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/memmap.h 1 file changed, 3 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/46993/1 diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index ac3b1db..0ff7b52 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -3,13 +3,9 @@ #ifndef __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ #define __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ -/* Intel Enhanced Debug region */ -#define IED_SIZE CONFIG_IED_REGION_SIZE - -/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_MCHBAR 0xfed10000 +#define DEFAULT_DMIBAR 0xfed18000 +#define DEFAULT_EPBAR 0xfed19000 #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 -- To view, visit https://review.coreboot.org/c/coreboot/+/46993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16033b558fe4c01a9394382dc0c9d0bdc66193d9 Gerrit-Change-Number: 46993 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] soc/intel/broadwell: Clean up some headers
by Angel Pons (Code Review) 05 Jan '21

05 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46798 ) Change subject: [WIP] soc/intel/broadwell: Clean up some headers ...................................................................... [WIP] soc/intel/broadwell: Clean up some headers Change-Id: Ib24539a11ca78eebb43f7fe17eeac7901aba79b8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/acpi.c M src/soc/intel/broadwell/cpu/bootblock.c M src/soc/intel/broadwell/cpu/cpu.c R src/soc/intel/broadwell/cpu/haswell.h M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/cpu/smmrelocate.c M src/soc/intel/broadwell/cpu/tsc_freq.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/include/soc/acpi.h D src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/report_platform.c 16 files changed, 70 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46798/1 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 9b5ac9e..3927d3d 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -17,10 +17,8 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> diff --git a/src/soc/intel/broadwell/cpu/acpi.c b/src/soc/intel/broadwell/cpu/acpi.c index ec3d588..042049d 100644 --- a/src/soc/intel/broadwell/cpu/acpi.c +++ b/src/soc/intel/broadwell/cpu/acpi.c @@ -17,14 +17,13 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> +#include "haswell.h" /* * List of supported C-states in this processor. Only the ULT parts support C8, diff --git a/src/soc/intel/broadwell/cpu/bootblock.c b/src/soc/intel/broadwell/cpu/bootblock.c index d6883c6..6460b69 100644 --- a/src/soc/intel/broadwell/cpu/bootblock.c +++ b/src/soc/intel/broadwell/cpu/bootblock.c @@ -6,8 +6,8 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <soc/rcba.h> -#include <soc/msr.h> #include <delay.h> +#include "haswell.h" static void set_flex_ratio_to_tdp_nominal(void) { diff --git a/src/soc/intel/broadwell/cpu/cpu.c b/src/soc/intel/broadwell/cpu/cpu.c index 72efa3d..036ca8c 100644 --- a/src/soc/intel/broadwell/cpu/cpu.c +++ b/src/soc/intel/broadwell/cpu/cpu.c @@ -15,14 +15,13 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> #include <delay.h> -#include <soc/cpu.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> +#include "haswell.h" /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/cpu/haswell.h similarity index 60% rename from src/soc/intel/broadwell/include/soc/msr.h rename to src/soc/intel/broadwell/cpu/haswell.h index 6a5f4dc..0f01457 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/cpu/haswell.h @@ -1,7 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _BROADWELL_MSR_H_ -#define _BROADWELL_MSR_H_ +#ifndef _CPU_BROADWELL_H_ +#define _CPU_BROADWELL_H_ + +#include <arch/cpu.h> +#include <stdint.h> + +/* CPU types */ +#define HASWELL_FAMILY_ULT 0x40650 +#define BROADWELL_FAMILY_ULT 0x306d0 + +/* Supported CPUIDs */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT 0x40651 +#define CPUID_HASWELL_HALO 0x40661 +#define CPUID_BROADWELL_C0 0x306d2 +#define CPUID_BROADWELL_D0 0x306d3 +#define CPUID_BROADWELL_E0 0x306d4 + +/* CPU bus clock is fixed at 100MHz */ +#define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce @@ -75,4 +96,39 @@ #define SMRR_SUPPORTED (1<<11) #define PRMRR_SUPPORTED (1<<12) +/* Latency times in units of 1024ns. */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); + +/* CPU identification */ +static inline u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + +static inline u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + #endif diff --git a/src/soc/intel/broadwell/cpu/romstage.c b/src/soc/intel/broadwell/cpu/romstage.c index c9f70a8..3434adf 100644 --- a/src/soc/intel/broadwell/cpu/romstage.c +++ b/src/soc/intel/broadwell/cpu/romstage.c @@ -3,9 +3,8 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> #include <soc/romstage.h> +#include "haswell.h" void set_max_freq(void) { diff --git a/src/soc/intel/broadwell/cpu/smmrelocate.c b/src/soc/intel/broadwell/cpu/smmrelocate.c index 3d4162a..df46f80 100644 --- a/src/soc/intel/broadwell/cpu/smmrelocate.c +++ b/src/soc/intel/broadwell/cpu/smmrelocate.c @@ -13,10 +13,9 @@ #include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <smp/node.h> -#include <soc/cpu.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include "haswell.h" static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/broadwell/cpu/tsc_freq.c b/src/soc/intel/broadwell/cpu/tsc_freq.c index 4a8a343..fab1909 100644 --- a/src/soc/intel/broadwell/cpu/tsc_freq.c +++ b/src/soc/intel/broadwell/cpu/tsc_freq.c @@ -2,8 +2,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <soc/cpu.h> -#include <soc/msr.h> +#include "haswell.h" unsigned long tsc_freq_mhz(void) { diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index d42eebc..07b3ff8 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -15,7 +15,6 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> -#include <soc/cpu.h> #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> @@ -23,6 +22,7 @@ #include <security/vboot/vbnv.h> #include <soc/igd.h> #include <types.h> +#include "cpu/haswell.h" #define GT_RETRY 1000 enum { diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 39d6cb4..97a37c7 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -6,12 +6,6 @@ #include <acpi/acpi.h> #include <soc/nvs.h> -/* P-state configuration */ -#define PSS_MAX_ENTRIES 8 -#define PSS_RATIO_STEP 2 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 - unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp); #endif diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h deleted file mode 100644 index bc5d2d7..0000000 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_CPU_H_ -#define _BROADWELL_CPU_H_ - -#include <arch/cpu.h> -#include <device/device.h> -#include <stdint.h> - -/* CPU types */ -#define HASWELL_FAMILY_ULT 0x40650 -#define BROADWELL_FAMILY_ULT 0x306d0 - -/* Supported CPUIDs */ -#define CPUID_HASWELL_A0 0x306c1 -#define CPUID_HASWELL_B0 0x306c2 -#define CPUID_HASWELL_C0 0x306c3 -#define CPUID_HASWELL_ULT_B0 0x40650 -#define CPUID_HASWELL_ULT 0x40651 -#define CPUID_HASWELL_HALO 0x40661 -#define CPUID_BROADWELL_C0 0x306d2 -#define CPUID_BROADWELL_D0 0x306d3 -#define CPUID_BROADWELL_E0 0x306d4 - -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - -/* Latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); - -/* CPU identification */ -static inline u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -static inline u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -#endif diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index b9aeb38..af9a826 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -10,11 +10,11 @@ #include <device/pci_ids.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include "cpu/haswell.h" u8 systemagent_revision(void) { diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 712bb46..9b20d89 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -17,10 +17,8 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index c98201e..99b3310 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -14,8 +14,8 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> -#include <soc/cpu.h> #include <delay.h> +#include "../cpu/haswell.h" /* Low Power variant has 6 root ports. */ #define MAX_NUM_ROOT_PORTS 6 diff --git a/src/soc/intel/broadwell/pch/xhci.c b/src/soc/intel/broadwell/pch/xhci.c index baaf5ba..5036cd8 100644 --- a/src/soc/intel/broadwell/pch/xhci.c +++ b/src/soc/intel/broadwell/pch/xhci.c @@ -9,7 +9,8 @@ #include <device/pci_ops.h> #include <soc/ramstage.h> #include <soc/xhci.h> -#include <soc/cpu.h> +#include <arch/cpu.h> +#include "../cpu/haswell.h" #ifdef __SIMPLE_DEVICE__ static u8 *usb_xhci_mem_base(pci_devfn_t dev) diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index 4ed84d7..3bc1622 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -7,11 +7,11 @@ #include <string.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/systemagent.h> +#include "cpu/haswell.h" static struct { u32 cpuid; -- To view, visit https://review.coreboot.org/c/coreboot/+/46798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib24539a11ca78eebb43f7fe17eeac7901aba79b8 Gerrit-Change-Number: 46798 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/l140cu: Add vboot support
by Michael Niewöhner (Code Review) 05 Jan '21

05 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46602 ) Change subject: mb/clevo/l140cu: Add vboot support ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/fmds/vboot-roab.fmd: https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… PS5, Line 22: RW_VPD(PRESERVE) 0x2000 > I forgot to push. Sorry, for the confusion. ack, np :D -- To view, visit https://review.coreboot.org/c/coreboot/+/46602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb5e93eb55ece5b0e0d91b1a374d33e259c65cac Gerrit-Change-Number: 46602 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 20:16:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Add vboot support
by Felix Singer (Code Review) 05 Jan '21

05 Jan '21

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46602 ) Change subject: mb/clevo/l140cu: Add vboot support ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/fmds/vboot-roab.fmd: https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… PS5, Line 22: RW_VPD(PRESERVE) 0x2000 > ? I forgot to push. Sorry, for the confusion. -- To view, visit https://review.coreboot.org/c/coreboot/+/46602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb5e93eb55ece5b0e0d91b1a374d33e259c65cac Gerrit-Change-Number: 46602 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 20:15:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Add vboot support
by Felix Singer (Code Review) 05 Jan '21

05 Jan '21

Hello build bot (Jenkins), Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46602 to look at the new patch set (#8). Change subject: mb/clevo/l140cu: Add vboot support ...................................................................... mb/clevo/l140cu: Add vboot support Add proper vboot configuration and add fmap files for the following partition schemes: * read-only * read-only + updateable A partition * read-only + updateable A/B partition All partition schemes were tested and are working. Change-Id: Ibb5e93eb55ece5b0e0d91b1a374d33e259c65cac Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Kconfig A src/mainboard/clevo/cml-u/variants/l140cu/fmds/vboot-ro.fmd A src/mainboard/clevo/cml-u/variants/l140cu/fmds/vboot-roa.fmd A src/mainboard/clevo/cml-u/variants/l140cu/fmds/vboot-roab.fmd 4 files changed, 105 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/46602/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/46602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb5e93eb55ece5b0e0d91b1a374d33e259c65cac Gerrit-Change-Number: 46602 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/l140cu: Add vboot support
by Michael Niewöhner (Code Review) 05 Jan '21

05 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46602 ) Change subject: mb/clevo/l140cu: Add vboot support ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/fmds/vboot-roab.fmd: https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… PS5, Line 22: RW_VPD(PRESERVE) 0x2000 > Done ? -- To view, visit https://review.coreboot.org/c/coreboot/+/46602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb5e93eb55ece5b0e0d91b1a374d33e259c65cac Gerrit-Change-Number: 46602 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 20:12:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Add vboot support
by Felix Singer (Code Review) 05 Jan '21

05 Jan '21

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46602 ) Change subject: mb/clevo/l140cu: Add vboot support ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/46602/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46602/5//COMMIT_MSG@15 PS5, Line 15: > the filenames look odd to me: […] The A/B partitions are by definition updateable und thus read-write. So this doesn't add much value. https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/variants/l140cu/fmds/vboot-roab.fmd: https://review.coreboot.org/c/coreboot/+/46602/5/src/mainboard/clevo/cml-u/… PS5, Line 22: RW_VPD(PRESERVE) 0x2000 > result of discussion on IRQ with Tim and Matt: don't add the VPD region if we don't have concrete pl […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb5e93eb55ece5b0e0d91b1a374d33e259c65cac Gerrit-Change-Number: 46602 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 20:02:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Add INT[E-H] to FCH PIR
by Raul Rangel (Code Review) 05 Jan '21

05 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48664 ) Change subject: mb/google/zork: Add INT[E-H] to FCH PIR ...................................................................... mb/google/zork: Add INT[E-H] to FCH PIR INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC. BUG=b:170595019 TEST=Verify ezkinil still boots Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275 --- M src/mainboard/google/zork/mainboard.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48664/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index dce2eaf..824a87d 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -76,7 +76,14 @@ /* * This controls the device -> IRQ routing. - * The PIC values are limited to 0,1, 3 - 12, 14, 15. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 <- ec/google/chromeec/acpi/superio.asl + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + * 12: i8042 <- ec/google/chromeec/acpi/superio.asl */ static const struct fch_irq_routing { uint8_t intr_index; @@ -84,9 +91,14 @@ uint8_t apic_irq_num; } fch_pirq[] = { { PIRQ_A, 6, 16 }, - { PIRQ_B, 6, 17 }, + { PIRQ_B, 13, 17 }, { PIRQ_C, 14, 18 }, { PIRQ_D, 15, 19 }, + { PIRQ_E, 15, 20 }, + { PIRQ_F, 14, 21 }, + { PIRQ_G, 13, 22 }, + { PIRQ_H, 6, 23 }, + { PIRQ_SCI, 9, 9 }, { PIRQ_EMMC, 5, 5 }, { PIRQ_GPIO, 7, 7 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/48664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275 Gerrit-Change-Number: 48664 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/Makefile: Verify bootblock size is power of two
by Raul Rangel (Code Review) 05 Jan '21

05 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40808 ) Change subject: soc/amd/picasso/Makefile: Verify bootblock size is power of two ...................................................................... soc/amd/picasso/Makefile: Verify bootblock size is power of two Enabling caching for bootblock requires its size to be a power of two. This is because MTRRs have this requirement. BUG=b:153675909 TEST=Changed bootblock size and saw a build error Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idede916cbc75bb0fecd729219b92dc9046c23d78 --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/40808/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b04e1e9..d137aba 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -189,6 +189,12 @@ # This address must match the BOOTBLOCK logic in arch/x86/memlayout.ld. PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE))) +# MTRRs sizes must be a power of two. Ensure the bootblock has a compatible size +# so we can enable caching. +ifneq ($(call is-power-of-two,$(PSP_BIOSBIN_SIZE)),1) +$(error Bootblock size $(PSP_BIOSBIN_SIZE) is not a power of two.) +endif + # type = 0x63 ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS) -- To view, visit https://review.coreboot.org/c/coreboot/+/40808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idede916cbc75bb0fecd729219b92dc9046c23d78 Gerrit-Change-Number: 40808 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Add is-power-of-two
by Raul Rangel (Code Review) 05 Jan '21

05 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40765 ) Change subject: Makefile: Add is-power-of-two ...................................................................... Makefile: Add is-power-of-two It is sometimes necessary to verify if a CONFIG_ option is a power of two at build time. This adds a `make` function `is-power-of-two`. I chose to define all the values because it's the most straightforward way to do this with `make`. BUG=b:147042464 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I189a4c722996279e2d8940c566cb362f53ef92d8 --- M Makefile.inc 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/40765/1 diff --git a/Makefile.inc b/Makefile.inc index e315732..cbec2dd 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -133,6 +133,7 @@ # int-gt: 1 if the first values is greater than the second. 0 otherwise # int-eq: 1 if the two values are equal. 0 otherwise # int-align: align $1 to $2 units +# is-power-of-two:1 if value is a power of two # file-size: returns the filesize of the given file # tolower: returns the value in all lowercase # toupper: returns the value in all uppercase @@ -151,6 +152,15 @@ int-eq=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) = $(call _toint,$(word 2,$1)))) int-align=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A + $ \( $$B - \( $$A % $$B $ \) % $$B \) ) int-align-down=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A - $ $$A % $$B $ ) +power-of-twos := 0x00000001 0x00000002 0x00000004 0x00000008 \ +0x00000010 0x00000020 0x00000040 0x00000080 \ +0x00000100 0x00000200 0x00000400 0x00000800 \ +0x00001000 0x00002000 0x00004000 0x00008000 \ +0x00010000 0x00020000 0x00040000 0x00080000 \ +0x00100000 0x00200000 0x00400000 0x00800000 \ +0x01000000 0x02000000 0x04000000 0x08000000 \ +0x10000000 0x20000000 0x40000000 0x80000000 +is-power-of-two=$(if $(filter $(power-of-twos), $(shell printf "0x%08x" $1)),1) file-size=$(strip $(shell cat $1 | wc -c)) tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]') toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]') @@ -575,6 +585,8 @@ @printf " HOSTCC $(subst $(obj)/,,$(@))\n" $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< +APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py + CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage FUTILITY?=$(objutil)/futility/futility -- To view, visit https://review.coreboot.org/c/coreboot/+/40765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I189a4c722996279e2d8940c566cb362f53ef92d8 Gerrit-Change-Number: 40765 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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