coreboot-gerrit January 2021

coreboot-gerrit@coreboot.org

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6507 discussions

Change in coreboot[master]: [UNTESTED] mb/ocp/tiogapass: correct "POST complete" pad initial value
by Johnny Lin (Code Review) 06 Jan '21

06 Jan '21

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48670 ) Change subject: [UNTESTED] mb/ocp/tiogapass: correct "POST complete" pad initial value ...................................................................... Patch Set 18: > Patch Set 18: > > > Patch Set 18: > > > > > Patch Set 18: Code-Review+1 > > > > > > The GPIO can be pulled low > > > > I meant to say CB:48671 can pull low the GPIO, this change can initialize it to high. > > Thank you! Do you have that board and can you test it with CB:48670 and CB:48671? Yes, I gave both changes +1. -- To view, visit https://review.coreboot.org/c/coreboot/+/48670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f Gerrit-Change-Number: 48670 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Jan 2021 00:21:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: enable wake on EC MKBP interrupts
by Peter Marheine (Code Review) 06 Jan '21

06 Jan '21

Peter Marheine has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48844 ) Change subject: mb/google/zork: enable wake on EC MKBP interrupts ...................................................................... mb/google/zork: enable wake on EC MKBP interrupts The EC generates EC_MKBP_EVENT_DP_ALT_MODE_ENTERED when USB-C connections enter DP alt mode, which should wake the system from S3. The EC signals these events via falling edge on EC_AP_INT_ODL, so this GPIO should be configured as a wake source. BUG=b:174121852 BRANCH=zork TEST=Manually-generated MKBP event (via EC console) wakes AP from S3. Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48844/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a2ad517..1a026e2 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -69,8 +69,8 @@ PAD_GPI(GPIO_29, PULL_NONE), /* FCH_ESPI_EC_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* EC_AP_INT_ODL (Sensor Framesync) */ - PAD_GPI(GPIO_31, PULL_NONE), + /* EC_AP_INT_ODL (mkbp interrupt) */ + PAD_WAKE(GPIO_31, PULL_NONE, EDGE_LOW, S3), /* GPIO_33 - GPIO_39: Not available */ /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), -- To view, visit https://review.coreboot.org/c/coreboot/+/48844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d Gerrit-Change-Number: 48844 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: {soc,vc,mb}/intel: Drop support for Cannon Lake SoC
by Tim Wawrzynczak (Code Review) 06 Jan '21

06 Jan '21

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48775 ) Change subject: {soc,vc,mb}/intel: Drop support for Cannon Lake SoC ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Gerrit-Change-Number: 48775 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 23:18:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Angel Pons (Code Review) 05 Jan '21

05 Jan '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… PS2, Line 552: /* Program XHCI SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } : : /* Program HDAudio SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } > It seems the xHCI and HDA devices end up writing 0, so they are set before calling SiliconInit. Could this be because FSP writes the `ssid_table` that this changes passes to it? -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 05 Jan 2021 21:57:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Furquan Shaikh (Code Review) 05 Jan '21

05 Jan '21

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 82: (1 comment) https://review.coreboot.org/c/coreboot/+/35402/82/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/35402/82/src/soc/intel/common/bloc… PS82, Line 19: depends on CHROMEOS > Yes, everything is clear now that we've discussed the topic with Tim. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 82 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Jan 2021 21:49:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/solidrun/solidpc: Do initial commit
by Felix Singer (Code Review) 05 Jan '21

05 Jan '21

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/23027 ) Change subject: mb/solidrun/solidpc: Do initial commit ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/23027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Gerrit-Change-Number: 23027 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/solidrun/solidpc: Do initial commit
by Felix Singer (Code Review) 05 Jan '21

05 Jan '21

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23027 ) Change subject: mb/solidrun/solidpc: Do initial commit ...................................................................... Patch Set 12: It seems that there is no interest in this anymore. Since I don't have this board, I will abandon it. If anyone wants to continue the work, this patch is still on Gerrit. -- To view, visit https://review.coreboot.org/c/coreboot/+/23027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Gerrit-Change-Number: 23027 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Tue, 05 Jan 2021 21:33:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 05 Jan '21

05 Jan '21

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 05 Jan '21

05 Jan '21

Hello build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49104 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit Prevent the FSP from writing the default SVID SDID values for internal devices as this locks the registers. Allows subsystemid values set in devicetree to be used. A description of this behavior, along with example code, is provided in the TigerLake FSP Integration Guide. Tested by checking lspci output on System76 galp3-c, oryp5, oryp6. Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49104/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...
by Tim Crawford (Code Review) 05 Jan '21

05 Jan '21

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… PS2, Line 550: 1 > What happens if setting this to zero? If set to 0 (default), then FspSiliconInit will write the default 8086:7270 value. https://review.coreboot.org/c/coreboot/+/49104/2/src/soc/intel/cannonlake/f… PS2, Line 552: /* Program XHCI SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_XHCI); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } : : /* Program HDAudio SSID/SVID before FSP silicon init */ : dev = pcidev_path_on_root(PCH_DEVFN_HDA); : if (!dev->subsystem_vendor || !dev->subsystem_device) { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : pci_read_config32(dev, PCI_VENDOR_ID)); : } else { : pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, : ((dev->subsystem_device & 0xffff) << 16) | : (dev->subsystem_vendor & 0xffff)); : } > Why is this needed? It seems the xHCI and HDA devices end up writing 0, so they are set before calling SiliconInit. -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 05 Jan 2021 21:23:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2021