coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel/braswell: Prevent NULL pointer dereference
by Angel Pons (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49359 to look at the new patch set (#2). Change subject: soc/intel/braswell: Prevent NULL pointer dereference ...................................................................... soc/intel/braswell: Prevent NULL pointer dereference Exit early if the chipset power state info isn't in CBMEM. Return -1 in order to ensure the one caller of this function exits early as well. Found-by: Coverity CID 1442304 Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/braswell/ramstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/49359/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf Gerrit-Change-Number: 49359 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/braswell: Avoid NULL pointer dereference
by Angel Pons (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: John Zhao, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49360 ) Change subject: soc/intel/braswell: Avoid NULL pointer dereference ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hmmm... I did CB:49359 already -- To view, visit https://review.coreboot.org/c/coreboot/+/49360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c3a919d607c2f1a25aef5726dc79f28484d19c0 Gerrit-Change-Number: 49360 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 16:48:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/amd/picasso/graphics: add RV1 PCI ID to VBIOS map code
by Felix Held (Code Review) 12 Jan '21

12 Jan '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49361 ) Change subject: [UNTESTED] soc/amd/picasso/graphics: add RV1 PCI ID to VBIOS map code ...................................................................... [UNTESTED] soc/amd/picasso/graphics: add RV1 PCI ID to VBIOS map code Change-Id: I2fc1a4d09da0776237a2fdc26f5b076343466d11 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/graphics.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/49361/1 diff --git a/src/soc/amd/picasso/graphics.c b/src/soc/amd/picasso/graphics.c index 047559c..10cdbc8 100644 --- a/src/soc/amd/picasso/graphics.c +++ b/src/soc/amd/picasso/graphics.c @@ -7,7 +7,7 @@ void map_oprom_vendev_rev(u32 *vendev, u8 *rev) { - if (*vendev != PICASSO_VBIOS_VID_DID) + if (*vendev != PICASSO_VBIOS_VID_DID && *vendev != RAVEN1_VBIOS_VID_DID) return; /* Check if the RV2 video bios needs to be used instead of the RV1/PCO one */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fc1a4d09da0776237a2fdc26f5b076343466d11 Gerrit-Change-Number: 49361 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/uart: Add ACPI SPCR table generation
by Raul Rangel (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Lance Zhao, Martin Roth. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49317 ) Change subject: drivers/uart: Add ACPI SPCR table generation ...................................................................... Patch Set 4: (2 comments) File src/include/acpi/acpi_device.h: https://review.coreboot.org/c/coreboot/+/49317/comment/5540f4a2_c77d10e3 PS4, Line 476: flow_control I don't see this one in the spec https://review.coreboot.org/c/coreboot/+/49317/comment/e4b89fe2_b8ab91b8 PS4, Line 503: (1 << 0) nit: BIT macro? -- To view, visit https://review.coreboot.org/c/coreboot/+/49317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a Gerrit-Change-Number: 49317 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 16:39:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: Avoid NULL pointer dereference
by John Zhao (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49360 to look at the new patch set (#2). Change subject: soc/intel/braswell: Avoid NULL pointer dereference ...................................................................... soc/intel/braswell: Avoid NULL pointer dereference Coverity detects dereference pointer ps that might be "NULL" when calling cbme_find function. Add sanity check for ps to prevent NULL pointer dereference. Found-by: Coverity CID 1442304 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I9c3a919d607c2f1a25aef5726dc79f28484d19c0 --- M src/soc/intel/braswell/ramstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/49360/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c3a919d607c2f1a25aef5726dc79f28484d19c0 Gerrit-Change-Number: 49360 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/braswell: Avoid NULL pointer dereference
by John Zhao (Code Review) 12 Jan '21

12 Jan '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49360 ) Change subject: soc/intel/braswell: Avoid NULL pointer dereference ...................................................................... soc/intel/braswell: Avoid NULL pointer dereference Coverity detects dereference pointer ps that might be "NULL" when calling cbme_find function. Add sanity check for ps to prevent NULL pointer dereference. Found-by: Coverity CID 1442304 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I9c3a919d607c2f1a25aef5726dc79f28484d19c0 --- M src/soc/intel/braswell/ramstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/49360/1 diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 7b92c52..b76a890 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -125,6 +125,9 @@ struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); static uint32_t gpe0_sts; + if (!ps) + return -1; + *pm1 = ps->pm1_sts & ps->pm1_en; gpe0_sts = ps->gpe0_sts & ps->gpe0_en; -- To view, visit https://review.coreboot.org/c/coreboot/+/49360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c3a919d607c2f1a25aef5726dc79f28484d19c0 Gerrit-Change-Number: 49360 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add option to stub out Global NVS
by Angel Pons (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Lance Zhao, Martin Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49278 ) Change subject: acpi: Add option to stub out Global NVS ...................................................................... Patch Set 1: (1 comment) File src/acpi/gnvs.c: https://review.coreboot.org/c/coreboot/+/49278/comment/ef53e9d0_316da53e PS1, Line 14: if (CONFIG(ACPI_NO_GLOBAL_NVS_SUPPORT)) : return NULL; > Why not totally exclude the gnvs. […] Ah yes, I could exclude the whole file. I'm waiting for Kyösti's patch train to go in before revisiting these changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/49278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie31f02c9e279e47ff10562bb077367d4e33f4dd9 Gerrit-Change-Number: 49278 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 16:15:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: Prevent NULL pointer dereference
by Angel Pons (Code Review) 12 Jan '21

12 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49359 ) Change subject: soc/intel/braswell: Prevent NULL pointer dereference ...................................................................... soc/intel/braswell: Prevent NULL pointer dereference Exit early if the chipset power state info isn't in CBMEM. Return -1 in order to ensure the one caller of this function exits early as well. Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/braswell/ramstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/49359/1 diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 7b92c52..de90cb7 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -125,6 +125,9 @@ struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); static uint32_t gpe0_sts; + if (!ps) + return -1; + *pm1 = ps->pm1_sts & ps->pm1_en; gpe0_sts = ps->gpe0_sts & ps->gpe0_en; -- To view, visit https://review.coreboot.org/c/coreboot/+/49359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf Gerrit-Change-Number: 49359 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/uart: Add ACPI SPCR table generation
by Martin Roth (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Lance Zhao, Martin Roth. Hello Lance Zhao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49317 to look at the new patch set (#4). Change subject: drivers/uart: Add ACPI SPCR table generation ...................................................................... drivers/uart: Add ACPI SPCR table generation The SPCR ACPI table is used to indicate whether a serial port or a non-legacy UART interface is available for use with Microsoft Windows Emergency Management Services (EMS). It is also used by Linux and BITS to determine the serial port configuration. For more information, see the Reference Serial Port Console Redirection Table. https://web.archive.org/web/20210111235235/https://docs.microsoft.com/en-us… BUG=b:74392237 TEST=Build Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a --- M src/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/uart/acpi/chip.h M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/drivers/uart/util.c M src/include/acpi/acpi.h M src/include/acpi/acpi_device.h M src/include/console/uart.h 9 files changed, 247 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/49317/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a Gerrit-Change-Number: 49317 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Lance Zhao Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Use GOS() to detect HPET visibility
by Angel Pons (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Kyösti Mälkki, Alexander Couzens, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49350 ) Change subject: Use GOS() to detect HPET visibility ...................................................................... Patch Set 1: Code-Review-1 (2 comments) Patchset: PS1: Th File src/southbridge/intel/common/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/49350/comment/c4bbf4f4_bd0dbb5c PS1, Line 98: } This change was done earlier but had to be reverted as it caused regressions: CB:41192 -- To view, visit https://review.coreboot.org/c/coreboot/+/49350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50ba3c836f62cbeea97a1f73e5229f777a4ba296 Gerrit-Change-Number: 49350 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 15:59:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2021