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Change subject: sb/intel: Select ACPI_SOC_NVS where suitable
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49344/comment/37b3e46e_43683deb
PS2, Line 7: sb/intel: Select ACPI_SOC_NVS where suitable
I see some AMD changes as well, maybe update the commit summary?
Patchset:
PS2:
While I do not like the "soc" thing everywhere, I'll find some way to get rid of it.
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Change subject: sb/intel: Add CBMC entries in GNVS
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Does anything use the CBMC field in GNVS?
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Change subject: soc/intel/*: drop UART pad configuration from common code
......................................................................
Patch Set 10: Code-Review+1
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Change subject: mb/google/dedede/var/boten: Update LTE GPIO configuration
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48623/comment/add1cd4f_85765d16
PS3, Line 9: LTE module is not expected to be powered off during warm reset
> Is there any expectation w.r.t. […]
Does the kernel load FW for the module? The enable & reset GPIOs are passed to the kernel, so it could do the power sequencing for FW updates
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Hello build bot (Jenkins), Martin Roth, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49358
to look at the new patch set (#2).
Change subject: build system: Structure and serialize INTERMEDIATE
......................................................................
build system: Structure and serialize INTERMEDIATE
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying
the file in some way. When running them in parallel, coreboot.pre can be
read from and written to in parallel which can corrupt the result.
Add a function to create those rules that also adds existing
INTERMEDIATE targets to enforce an order (as established by evaluation
order of Makefile.inc files).
While at it, also add the addition to the PHONY target so we don't
forget it.
BUG=chromium:1154313, b:174585424
TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2
timeout and sercon) and saw that they were executed.
Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M Makefile.inc
M payloads/external/Makefile.inc
M src/cpu/intel/fit/Makefile.inc
M src/ec/hp/kbc1126/Makefile.inc
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/amd/mandolin/Makefile.inc
M src/security/intel/cbnt/Makefile.inc
M src/security/intel/txt/Makefile.inc
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/intel/common/block/fast_spi/Makefile.inc
M src/southbridge/amd/pi/hudson/Makefile.inc
M src/southbridge/intel/common/firmware/Makefile.inc
12 files changed, 22 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/49358/2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49318 )
Change subject: nb/intel/sandybridge: Remove wrong and nonsense condition
......................................................................
Patch Set 1: -Code-Review
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49318/comment/76e618e7_df51206f
PS1, Line 10: comment that says the opposite
> Argh, let me revise it again...
# Programming Command, Control, Clock
CMD is a single setting, shared across all ranks.
CTL is per DIMM, and we use the average for dual-rank DIMMs.
CLK is per rank, and needs the extra `pi_code_offset`. CB:49319
If some ranks have a negative `pi_coding` value, determine the most negative `pi_coding` value among all populated ranks, save it as `min_pi_code`, then program:
* CMD = -min_pi_code;
* CTL = -min_pi_code + pi_coding;
* CLK = -min_pi_code + pi_coding + pi_code_offset;
If all `pi_coding` values are positive, `min_pi_code` is zero:
* CMD = 0;
* CTL = pi_coding;
* CLK = pi_coding + pi_code_offset;
# Data training fix (what CB:49067 does)
After adjusting CCC (CMD, CTL, CLK), the data training result needs to be corrected, per rank. This correction involves incrementing the TxDQ, TxDQS, RcvEn timings by `-min_pi_code + pi_coding` (the theoretical value for CTL).
Note that the rank's I/O and roundtrip latencies need to be adjusted accordingly when changing the RcvEn timings. This involves five steps:
1. Compute the difference between the smallest and largest RcvEn logic delays of the current rank. Let's call it `delta_prev`.
2. For all lanes of the current rank, adjust the RcvEn timings as required.
3. Find the smallest RcvEn logic delay (whole number of QCLKs) among all lanes (of the current rank). Then, decrement the I/O latency and RcvEn of all lanes of the current rank by this amount of QCLKs.
4. Compute the difference between the smallest and largest RcvEn logic delays of the current rank, again. Let's call it `delta_post`.
5. If `delta_post < delta_prev`, decrease the current rank's I/O and roundtrip latencies by one. Else if `delta_post > delta_prev`, increase the current rank's I/O and roundtrip latencies by one.
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