coreboot-gerrit January 2021

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Change in coreboot[master]: nb/intel/sandybridge: Correct description of QCLK
by Nico Huber (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49363 ) Change subject: nb/intel/sandybridge: Correct description of QCLK ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: The old text seems to make more sense, why should it be one half? -- To view, visit https://review.coreboot.org/c/coreboot/+/49363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7089fc32381addc280a71761a377075f107b5c62 Gerrit-Change-Number: 49363 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 21:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: spd: Create new folder for SPD files
by Tim Wawrzynczak (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49338 ) Change subject: spd: Create new folder for SPD files ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > woops,link not allowed […] weird.... anyone have any idea why they're not allowed? Another way I could think of is to have a Kconfig per-platform that points to the appropriate SPD directory -- To view, visit https://review.coreboot.org/c/coreboot/+/49338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a871981642485020adaeaafd062f718c636a708 Gerrit-Change-Number: 49338 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 21:37:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/pineview: Extract HPET setup and delay function
by Angel Pons (Code Review) 12 Jan '21

12 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49365 ) Change subject: nb/intel/pineview: Extract HPET setup and delay function ...................................................................... nb/intel/pineview: Extract HPET setup and delay function To allow other platforms to reuse this code, extract it into a separate compilation unit. Since HPET is enabled through the southbridge, place the code in the southbridge scope. Finally, select the newly-added Kconfig option from i82801gx and replace lpc.c `enable_hpet` function. Change-Id: I7a28cc4d12c6d79cd8ec45dfc8100f15e6eac303 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/raminit.c M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/hpet.c A src/southbridge/intel/common/hpet.h M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/lpc.c 7 files changed, 62 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/49365/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 2248d03..dd728e8 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <delay.h> #include <lib.h> +#include <southbridge/intel/common/hpet.h> #include "pineview.h" #include "raminit.h" #include <spd.h> @@ -529,20 +530,6 @@ } } -#define HPET_BASE 0xfed00000 -#define HPET32(x) *((volatile u32 *)(HPET_BASE + x)) -static void enable_hpet(void) -{ - u32 reg32; - reg32 = RCBA32(HPTC); - reg32 &= ~0x03; - reg32 |= (1 << 7); - RCBA32(HPTC) = reg32; - /* On NM10 this only works if read back */ - RCBA32(HPTC); - HPET32(0x10) = HPET32(0x10) | 1; -} - static void sdram_clk_crossing(struct sysinfo *s) { u8 ddr_freq, fsb_freq; @@ -1595,27 +1582,6 @@ pci_write_config32(HOST_BRIDGE, 0xac, tsegmb[s->dimm_config[0]]); } -static void hpet_udelay(u32 del) -{ - u32 start, finish, now; - - del *= 15; /* now in usec */ - - start = HPET32(0xf0); - finish = start + del; - while (1) { - now = HPET32(0xf0); - if (finish > start) { - if (now >= finish) - break; - } else { - if ((now < start) && (now >= finish)) { - break; - } - } - } -} - static u8 sdram_checkrcompoverride(void) { u32 xcomp; diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 3030d25..a14513d 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n +config SOUTHBRIDGE_INTEL_COMMON_HPET + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 6c57481..f11ffa6 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -5,6 +5,8 @@ all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET) += hpet.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/common/hpet.c b/src/southbridge/intel/common/hpet.c new file mode 100644 index 0000000..c48edae --- /dev/null +++ b/src/southbridge/intel/common/hpet.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/rcba.h> +#include <stdint.h> + +#include "hpet.h" + +#define HPTC 0x3404 + +#define HPET_BASE 0xfed00000 +#define HPET32(x) (*((volatile u32 *)(HPET_BASE + (x)))) + +void enable_hpet(void) +{ + u32 reg32; + reg32 = RCBA32(HPTC); + reg32 &= ~0x03; + reg32 |= (1 << 7); + RCBA32(HPTC) = reg32; + /* Read back for posted write to take effect */ + RCBA32(HPTC); + HPET32(0x10) = HPET32(0x10) | 1; +} + +void hpet_udelay(u32 delay) +{ + u32 start, finish, now; + + delay *= 15; /* now in usec */ + + start = HPET32(0xf0); + finish = start + delay; + while (1) { + now = HPET32(0xf0); + if (finish > start) { + if (now >= finish) + break; + } else { + if ((now < start) && (now >= finish)) + break; + } + } +} diff --git a/src/southbridge/intel/common/hpet.h b/src/southbridge/intel/common/hpet.h new file mode 100644 index 0000000..1a69178 --- /dev/null +++ b/src/southbridge/intel/common/hpet.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_HPET_H +#define SOUTHBRIDGE_INTEL_COMMON_HPET_H + +#include <stdint.h> + +void enable_hpet(void); +void hpet_udelay(u32 delay); + +#endif /* SOUTHBRIDGE_INTEL_COMMON_HPET_H */ diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d3bf24..2cd56e9 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -21,6 +21,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_HPET if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 5438b00..153065b 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -18,6 +18,7 @@ #include <arch/smp/mpspec.h> #include <string.h> #include <southbridge/intel/common/acpi_pirq_gen.h> +#include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/spi.h> @@ -268,21 +269,6 @@ cmos_init(rtc_failed); } -static void enable_hpet(void) -{ - u32 reg32; - - /* Move HPET to default address 0xfed00000 and enable it */ - reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable - reg32 &= ~(3 << 0); - RCBA32(HPTC) = reg32; - /* On NM10 this only works if read back */ - RCBA32(HPTC); - - write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); -} - static void enable_clock_gating(void) { u32 reg32; -- To view, visit https://review.coreboot.org/c/coreboot/+/49365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a28cc4d12c6d79cd8ec45dfc8100f15e6eac303 Gerrit-Change-Number: 49365 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Initiate overridetree.cb
by EricR Lai (Code Review) 12 Jan '21

12 Jan '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48794 ) Change subject: mb/google/brya: Initiate overridetree.cb ...................................................................... mb/google/brya: Initiate overridetree.cb Initiate overridetree.cb based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I31e5ac1703476083ac71dac30b0a3299b38384c0 --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 224 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48794/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 2989621..41105e1 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,6 +1,9 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9324 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb new file mode 100644 index 0000000..c82a1b2 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -0,0 +1,221 @@ +chip soc/intel/alderlake + register "SaGv" = "SaGv_Disabled" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SIS9815"" + register "generic.desc" = ""SIS Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "100" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 5c on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 28 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + end + end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref pmc hidden end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/48794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e5ac1703476083ac71dac30b0a3299b38384c0 Gerrit-Change-Number: 48794 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add gpio table
by EricR Lai (Code Review) 12 Jan '21

12 Jan '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48290 ) Change subject: mb/google/brya: Add gpio table ...................................................................... mb/google/brya: Add gpio table Follow latest schematic to fill gpio table. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I3a983605b5139ff8510a0cf225e6564b9215cb1a --- M src/mainboard/google/brya/variants/baseboard/gpio.c 1 file changed, 372 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/48290/1 diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index 39450ce..41dab2f 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -6,12 +6,382 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + /* A0 thru A5 and A9 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_ALERT0# ==> ESPI_ALERT_AP_L */ + /* A6 : ESPI_ALERT1# ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_A6, NONE, DEEP), + /* A7 : SRCCLK_OE7# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, LEVEL, INVERT), + /* A8 : SRCCLKREQ7# ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : ESPI_CLK ==> ESPI_CLK */ + /* A10 : ESPI_RESET# ==> NC */ + PAD_NC(GPP_A10, NONE), + /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF4), /// NF4? + /* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF4), /// NF4? + /* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /// NF1? + /* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /// NF1? + /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */ + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH), + + /* B0 : SOC_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : SOC_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : NC ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* B9 : NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : TIME_SYNC0 ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_B15, 1, DEEP), + /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ + PAD_NC(GPP_B18, NONE), + /* B19 : NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ + PAD_NC(GPP_B23, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : SML0CLK ==> EN_PP3300_TCHPAD */ + PAD_CFG_GPO(GPP_C3, 1, DEEP), + /* C4 : SML0DATA ==> EN_PP5000_TCHPAD */ + PAD_CFG_GPO(GPP_C4, 1, DEEP), + /* C5 : SML0ALERT# ==> GPP_C25_BOOT_STRAP0 */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1CLK ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_C6, 0, DEEP), + /* C7 : SML1DATA ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), + + /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : ISH_GP3 ==> WCAM_RST_L */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_D5, 1, DEEP), + /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + PAD_NC(GPP_D12, NONE), + /* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), + /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), + /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), + /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), /// should low in early table + /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_E1, NONE, DEEP), + /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : PROC_GP0 ==> HPS_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), ///how to use this pin? camera? + /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), + /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 0, DEEP), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : PROC_GP1 ==> EN_HPS_PWR */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_E8, 1, DEEP), + /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_E10, NONE, DEEP), + /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_E17, NONE, DEEP), + /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P: Retimer FW drives this pin */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N: Retimer FW drives this pin */ + PAD_NC(GPP_E23, NONE), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : NC */ + PAD_NC(GPP_F8, NONE), + /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /// NF1?? + /* F10 : GPPF10_STRAP */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, DEEP, LEVEL, INVERT), + /* F15 : GSXSRESET# ==> FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), // wake? + /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_F17, NONE, PLTRST, LEVEL, INVERT), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_F19, NONE, DEEP), + /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F21, NONE, DEEP, LEVEL, INVERT), // what type of trigger? + /* F22 : NC */ + PAD_NC(GPP_F22, NONE), + /* F23 : NC */ + PAD_NC(GPP_F23, NONE), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_H3, NONE, DEEP), + /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX2 */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX1 */ + PAD_NC(GPP_H9, NONE), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H14 : NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H16 : NC */ + PAD_NC(GPP_H16, NONE), + /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : SRCCLKREQ4# ==> SAR_INT_L */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* H21 : IMGCLKOUT2 ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_H21, NONE, DEEP, EDGE_SINGLE), + /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), + + /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S4 : SNDW2_CLK ==> SDW_SPKR_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* S5 : SNDW2_DATA ==> SDW_SPKR_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_CFG_GPI(GPD7, DN_20K, DEEP), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L_CAP_SITE */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configuration */ + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + + /* B8 : NC ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), }; const struct pad_config *__weak variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/48290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a983605b5139ff8510a0cf225e6564b9215cb1a Gerrit-Change-Number: 48290 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: soc/intel/common: Move L1_substates_control to pcie_rp.h
by Tim Wawrzynczak (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49295 ) Change subject: soc/intel/common: Move L1_substates_control to pcie_rp.h ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: needs a rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/49295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Gerrit-Change-Number: 49295 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 21:12:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Update PL1 min and max for Delbin
by Deepika Punyamurtula (Code Review) 12 Jan '21

12 Jan '21

Deepika Punyamurtula has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49364 ) Change subject: mb/google/volteer/variants/delbin: Update PL1 min and max for Delbin ...................................................................... mb/google/volteer/variants/delbin: Update PL1 min and max for Delbin Update PL1 min and max values for Delbin systems BUG=b:168958222 BRANCH=None TEST=Build and verify on delbin system Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Change-Id: I2152f0dbeb0ae463b78464571b6c434830f0082a --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/49364/1 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index aa06d09..5e9600b 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -69,7 +69,7 @@ register "tcc_offset" = "8" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 15, + .tdp_pl1_override = 18, .tdp_pl2_override = 51, .tdp_pl4 = 105, }" @@ -104,11 +104,11 @@ [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 80, SHUTDOWN)}" ## Power Limits Control - # 3-15W PL1 in 200mW increments, avg over 28-32s interval - # PL2 is 15-51W, avg over 28-32s interval + # 12-18W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is 51W, avg over 28-32s interval register "controls.power_limits" = "{ - .pl1 = {.min_power = 3000, - .max_power = 15000, + .pl1 = {.min_power = 12000, + .max_power = 18000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, -- To view, visit https://review.coreboot.org/c/coreboot/+/49364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2152f0dbeb0ae463b78464571b6c434830f0082a Gerrit-Change-Number: 49364 Gerrit-PatchSet: 1 Gerrit-Owner: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Disable TC cold support
by Nick Vaccaro (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: John Zhao, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Disable TC cold support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 20:40:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Correct description of QCLK
by Angel Pons (Code Review) 12 Jan '21

12 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49363 ) Change subject: nb/intel/sandybridge: Correct description of QCLK ...................................................................... nb/intel/sandybridge: Correct description of QCLK QCLK means "quadrature clock", and is equivalent to one half of a full clock cycle (tCK). Fix the comment. The `QCLK_PI` value is still valid. Change-Id: I7089fc32381addc280a71761a377075f107b5c62 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/49363/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 0015a09..8126ce8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -434,7 +434,8 @@ #define MIN_CAS 4 /* - * 1 QCLK (quarter of a clock cycle) equals 64 PI (phase interpolator) ticks. + * 1 QCLK (quadrature clock) is one half of a full clock cycle (tCK). + * In addition, 64 PI (phase interpolator) ticks are equal to 1 QCLK. * Logic delay values in I/O register bitfields are expressed in QCLKs. */ #define QCLK_PI 64 -- To view, visit https://review.coreboot.org/c/coreboot/+/49363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7089fc32381addc280a71761a377075f107b5c62 Gerrit-Change-Number: 49363 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Angel Pons. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 6: (1 comment) File Documentation/mainboard/system76/oryp5.md: https://review.coreboot.org/c/coreboot/+/47892/comment/ac72f76f_62a2f312 PS5, Line 12: - eDP 16.1" or 17.3" 1920x1080 @ 144 Hz LCD > I suspect the backlight is currently controlled through i915's own backlight interface in sysfs. Setting backlight level works using the brightness slider in display settings. It does not work though keyboard shortcuts. -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 19:42:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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