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Change subject: WIP: soc/mediatek/mt8192: pmic: add scp voltage initialization
......................................................................
WIP: soc/mediatek/mt8192: pmic: add scp voltage initialization
Add scp voltage initialization.
BUG=none
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com>
Change-Id: I68302715ae804fed11bb54f4dfc4e90cde5224df
---
M src/soc/mediatek/mt8192/mt6359p.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/49355/2
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Change subject: ec/google/chromeec: Provide EC access path for Retimer firmware update
......................................................................
ec/google/chromeec: Provide EC access path for Retimer firmware update
Kernel needs to access EC RFWU entry in order to retrieve from EC about
port and mux info and set EC operations like modes change. This change
provides EC RFWU path for Retimer driver usage.
BUG=b:162528867
TEST=Booted to kernel and verified EC RFWU path from ACPI SSDT table.
Signed-off-by: John Zhao <john.zhao(a)intel.com>
Change-Id: I3817d93cfdeedf15825dab6c537b151fd063338b
---
M src/ec/google/chromeec/ec_acpi.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/49257/2
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Change subject: mb/google/volteer/variants/delbin: Update PL1 min and max for Delbin
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/dedede/var/boten: Update gpio config for boten
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/dedede/variants/boten/gpio.c:
https://review.coreboot.org/c/coreboot/+/49348/comment/39c68136_e6806b50
PS2, Line 54: PAD_CFG_GPO(GPP_B7, 1, DEEP),
GPP_B7 configuration is under GPP_A10 at line 12 should be better.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49358 )
Change subject: build system: Structure and serialize INTERMEDIATE
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
> I'm not too keen on hunting down parallel executions every time somebody adds a rule and forget to a […]
Well, I don't think anybody should directly dd to CBFS images anyway so you shouldn't really the flock utility. cbfstool is the only thing that should touch CBFS sections, and if other stuff needs to be written to other sections they should be clearly defined in the FMAP and written with cbfstool write, not just by juggling raw offsets in dd. I just didn't want to figure out how to rewrite all the old platforms but I don't think we should let new platforms do that anymore.
Anyway, I don't really mind if you want to serialize this anyway, this option seems a lot nicer than Martin's patch. If you do you might as well take the explicit flock calls in those rules back out again.
File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/49358/comment/d06b76ba_9494d879
PS2, Line 1151:
Why not add $(obj)/coreboot.pre right here so you don't have to do it explicitly everywhere? Modifying that file is the only point of these rules.
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Change subject: cbfs: Remove prog_locate() for stages and rmodules
......................................................................
Patch Set 2:
(1 comment)
File src/lib/cbfs.c:
https://review.coreboot.org/c/coreboot/+/49335/comment/740c51cb_17246d49
PS2, Line 393: if ((err = cbfs_boot_lookup(prog_name(pstage), false, &mdata, &rdev)))
do not use assignment in if condition
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Change subject: cbfs: Add cbfs_alloc() primitive and combine cbfs_load() and cbfs_map()
......................................................................
Patch Set 2:
(1 comment)
File src/lib/cbfs.c:
https://review.coreboot.org/c/coreboot/+/49334/comment/45930fc5_da0c20f7
PS2, Line 350: } else {
else is not generally useful after a break or return
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Change subject: soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguous
......................................................................
soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguous
In case of CPU PCIe RPs, the RP numbers might not be contiguous for
all the functions in a slot.
Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as
per the FSP expectations.
Hence, this change updates the defintion of `struct pcie_rp_group` to
include a `start` member which indicates the starting PCI function
number within the group. All common functions for PCIe RP are
accordingly updated to take the `start` member into account.
Thus, in the above example, ADL can provide a cpu_rp_table as follows:
{
{ .slot = PCIE_SLOT_6, .start = 0, .count = 1 },
{ .slot = PCIE_SLOT_1, .start = 0, .count = 1 },
{ .slot = PCIE_SLOT_6, .start = 2, .count = 1 },
}
Since start defaults to 0 when uninitialized, current PCH RP group
tables don't need to be updated.
Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
M src/soc/intel/common/block/pcie/pcie_helpers.c
M src/soc/intel/common/block/pcie/pcie_rp.c
3 files changed, 23 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/49370/1
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 264c43f..ecc5fcf 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -10,15 +10,27 @@
* functions.
*
* `slot` is the PCI device/slot number of such a group.
- * `count` is the number of functions within the group. It is assumed that
- * the first group includes the RPs 1 to the first group's `count` and that
- * adjacent groups follow without gaps in the numbering.
+ * `start` is the initial PCI function number within the group. This is useful in case the
+ * root port numbers are not contiguous within the slot.
+ * `count` is the number of functions within the group starting with the `start` function
+ * number.
*/
struct pcie_rp_group {
unsigned int slot;
+ unsigned int start;
unsigned int count;
};
+static inline unsigned int rp_start_fn(const struct pcie_rp_group *group)
+{
+ return group->start;
+}
+
+static inline unsigned int rp_end_fn(const struct pcie_rp_group *group)
+{
+ return group->start + group->count - 1;
+}
+
/*
* Update PCI paths of the root ports in the devicetree.
*
diff --git a/src/soc/intel/common/block/pcie/pcie_helpers.c b/src/soc/intel/common/block/pcie/pcie_helpers.c
index 31451d0..e8ed3be 100644
--- a/src/soc/intel/common/block/pcie/pcie_helpers.c
+++ b/src/soc/intel/common/block/pcie/pcie_helpers.c
@@ -5,14 +5,15 @@
#include <intelblocks/pcie_rp.h>
#include <stdint.h>
-static uint32_t pcie_slot_enable_mask(unsigned int slot, unsigned int count)
+static uint32_t pcie_slot_enable_mask(const struct pcie_rp_group *group)
{
uint32_t mask = 0;
+ unsigned int fn;
unsigned int i;
const struct device *dev;
- for (i = 0; i < count; i++) {
- dev = pcidev_on_root(slot, i);
+ for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) {
+ dev = pcidev_on_root(group->slot, fn);
if (is_dev_enabled(dev))
mask |= BIT(i);
}
@@ -32,7 +33,7 @@
__func__);
break;
}
- mask |= pcie_slot_enable_mask(group->slot, group->count) << offset;
+ mask |= pcie_slot_enable_mask(group) << offset;
offset += group->count;
}
diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c
index 85b218a..1c69f2c 100644
--- a/src/soc/intel/common/block/pcie/pcie_rp.c
+++ b/src/soc/intel/common/block/pcie/pcie_rp.c
@@ -54,7 +54,7 @@
const struct pcie_rp_group *group;
for (group = groups; group->count; ++group) {
unsigned int fn;
- for (fn = 0; fn < group->count; ++fn) {
+ for (fn = rp_start_fn(group); fn <= rp_end_fn(group); ++fn) {
const pci_devfn_t dev = PCI_DEV(0, group->slot, fn);
const uint16_t did = pci_s_read_config16(dev, PCI_DEVICE_ID);
if (did == 0xffff) {
@@ -96,7 +96,8 @@
const struct pcie_rp_group *group;
for (group = groups; group->count; ++group) {
if (PCI_SLOT(dev->path.pci.devfn) == group->slot &&
- PCI_FUNC(dev->path.pci.devfn) < group->count)
+ PCI_FUNC(dev->path.pci.devfn) >= rp_start_fn(group) &&
+ PCI_FUNC(dev->path.pci.devfn) <= rp_end_fn(group))
break;
offset += group->count;
}
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Change subject: memlayout: Store region sizes as separate symbols
......................................................................
Patch Set 2:
(3 comments)
File src/include/memlayout.h:
https://review.coreboot.org/c/coreboot/+/49332/comment/b5f1cde7_29cf5cd2
PS2, Line 36: #define RECORD_SIZE(name) \
Macros with multiple statements should be enclosed in a do - while loop
https://review.coreboot.org/c/coreboot/+/49332/comment/bcdec55e_208238a7
PS2, Line 36: #define RECORD_SIZE(name) \
macros should not use a trailing semicolon
https://review.coreboot.org/c/coreboot/+/49332/comment/d627148d_ba7d5739
PS2, Line 53: #define REGION_END(name, addr) \
Macros with complex values should be enclosed in parentheses
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