coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel: rename uart_max_index
by Furquan Shaikh (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49305 ) Change subject: soc/intel: rename uart_max_index ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7409c9dc040c3c6ad718abc96f268c187d50d79c Gerrit-Change-Number: 49305 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 19:27:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd_blobs: Add new picasso VBIOS
by Marshall Dawson (Code Review) 12 Jan '21

12 Jan '21

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49362 ) Change subject: amd_blobs: Add new picasso VBIOS ...................................................................... amd_blobs: Add new picasso VBIOS Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Icf1571ae360cee5698626f0360e1408360e8a7f6 --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/49362/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 2fe8e5a..b127449 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 2fe8e5a1e0ae1c4b5939e5a5afa6fa69308491f8 +Subproject commit b12744905dd20c77154db99a379543f61a3e3e7f -- To view, visit https://review.coreboot.org/c/coreboot/+/49362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf1571ae360cee5698626f0360e1408360e8a7f6 Gerrit-Change-Number: 49362 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Configure Voxel USB2 ports for Type C
by John Zhao (Code Review) 12 Jan '21

12 Jan '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49053 ) Change subject: mb/google/volteer: Configure Voxel USB2 ports for Type C ...................................................................... mb/google/volteer: Configure Voxel USB2 ports for Type C Two USB2 ports 4 and 9 are assigned to type C connectors on Voxel board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU which would allow a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Voxel board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ia370a449a41701e690c1c507d70bedfce2076a65 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/49053/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2caec2a..6ed3ff9 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -13,6 +13,9 @@ .tdp_pl4 = 105, }" + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Cl + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Co + # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" -- To view, visit https://review.coreboot.org/c/coreboot/+/49053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia370a449a41701e690c1c507d70bedfce2076a65 Gerrit-Change-Number: 49053 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Clean up program_timings
by Angel Pons (Code Review) 12 Jan '21

12 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47770 ) Change subject: nb/intel/sandybridge: Clean up program_timings ...................................................................... nb/intel/sandybridge: Clean up program_timings Clarify the clock, command and control programming sequence. Change-Id: I1aa4144197dc25dc8d6ef1d23e465280bddd95a3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 68 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/47770/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 399ba5a..e273c9b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -935,71 +935,89 @@ void program_timings(ramctr_timing *ctrl, int channel) { - u32 reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; + u32 reg_roundtrip_latency, reg_io_latency; int lane; int slotrank, slot; - int full_shift = 0; - u16 pi_coding_ctrl[NUM_SLOTS]; + u32 ctl_delay[NUM_SLOTS] = { 0 }; + int cmd_delay = 0; + + /* Enable CLK XOVER */ + u32 clk_pi_coding = get_XOVER_CLK(ctrl->rankmap[channel]); + u32 clk_logic_dly = 0; + + /* + * Apply command delay if desired setting is negative. Find the + * most negative value: 'cmd_delay' will be the absolute value. + */ FOR_ALL_POPULATED_RANKS { - if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) - full_shift = -ctrl->timings[channel][slotrank].pi_coding; + if (cmd_delay < -ctrl->timings[channel][slotrank].pi_coding) + cmd_delay = -ctrl->timings[channel][slotrank].pi_coding; + } + if (cmd_delay < 0) { + printk(BIOS_ERR, "C%d command delay underflow: %d\n", channel, cmd_delay); + cmd_delay = 0; + } + if (cmd_delay >= 128) { + printk(BIOS_ERR, "C%d command delay overflow: %d\n", channel, cmd_delay); + cmd_delay = 127; } - for (slot = 0; slot < NUM_SLOTS; slot++) - switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { - case 0: - default: - pi_coding_ctrl[slot] = 0x7f; - break; - case 1: - pi_coding_ctrl[slot] = - ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; - break; - case 2: - pi_coding_ctrl[slot] = - ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; - break; - case 3: - pi_coding_ctrl[slot] = - (ctrl->timings[channel][2 * slot].pi_coding + - ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; - break; + /* Apply control and clock delay if desired setting is positive */ + if (cmd_delay == 0) { + for (slot = 0; slot < NUM_SLOTS; slot++) { + const int pi_coding_0 = ctrl->timings[channel][2 * slot + 0].pi_coding; + const int pi_coding_1 = ctrl->timings[channel][2 * slot + 1].pi_coding; + + const u8 slot_map = (ctrl->rankmap[channel] >> (2 * slot)) & 3; + + if (slot_map & 1) + ctl_delay[slot] += pi_coding_0 + cmd_delay; + + if (slot_map & 2) + ctl_delay[slot] += pi_coding_1 + cmd_delay; + + if (slot_map == 3) + ctl_delay[slot] /= 2; + + if (ctl_delay[slot] >= 128) { + printk(BIOS_ERR, "C%dS%d control delay overflow: %d\n", + channel, slot, ctl_delay[slot]); + ctl_delay[slot] = 127; + } } + FOR_ALL_POPULATED_RANKS { + const u32 pi_delay = + ctrl->timings[channel][slotrank].pi_coding + cmd_delay; + u32 logic_delay = pi_delay / 64; + + if (logic_delay > 1) { + printk(BIOS_ERR, "C%dR%d clock delay overflow: %d\n", + channel, slotrank, pi_delay); + logic_delay = 1; + } + + clk_pi_coding |= (pi_delay % 64) << (6 * slotrank); + clk_logic_dly |= logic_delay << slotrank; + } + } /* Enable CMD XOVER */ union gdcr_cmd_pi_coding_reg cmd_pi_coding = { .raw = get_XOVER_CMD(ctrl->rankmap[channel]), }; - cmd_pi_coding.cmd_pi_code = full_shift & 0x3f; - cmd_pi_coding.cmd_logic_delay = !!(full_shift & 0x40); + cmd_pi_coding.cmd_pi_code = cmd_delay % 64; + cmd_pi_coding.cmd_logic_delay = cmd_delay / 64; - cmd_pi_coding.ctl_pi_code_d0 = pi_coding_ctrl[0] & 0x3f; - cmd_pi_coding.ctl_pi_code_d1 = pi_coding_ctrl[1] & 0x3f; - cmd_pi_coding.ctl_logic_delay_d0 = !!(pi_coding_ctrl[0] & 0x40); - cmd_pi_coding.ctl_logic_delay_d1 = !!(pi_coding_ctrl[1] & 0x40); + cmd_pi_coding.ctl_pi_code_d0 = ctl_delay[0] % 64; + cmd_pi_coding.ctl_pi_code_d1 = ctl_delay[1] % 64; + cmd_pi_coding.ctl_logic_delay_d0 = ctl_delay[0] / 64; + cmd_pi_coding.ctl_logic_delay_d1 = ctl_delay[1] / 64; MCHBAR32(GDCRCMDPICODING_ch(channel)) = cmd_pi_coding.raw; - /* Enable CLK XOVER */ - reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); - reg_logic_delay = 0; - - FOR_ALL_POPULATED_RANKS { - int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; - int offset_pi_code; - if (shift < 0) - shift = 0; - - offset_pi_code = ctrl->pi_code_offset + shift; - - /* Set CLK phase shift */ - reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); - reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; - } - - MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; - MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; + MCHBAR32(GDCRCKPICODE_ch(channel)) = clk_pi_coding; + MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = clk_logic_dly; reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); reg_io_latency &= ~0xffff; @@ -1010,7 +1028,7 @@ int post_timA_min_high = 7, pre_timA_min_high = 7; int post_timA_max_high = 0, pre_timA_max_high = 0; int shift_402x = 0; - int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][slotrank].pi_coding + cmd_delay; if (shift < 0) shift = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/47770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aa4144197dc25dc8d6ef1d23e465280bddd95a3 Gerrit-Change-Number: 47770 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: Enable EC keyboard backlight
by Karthik Ramasubramanian (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Henry Sun, Tim Chen, Ren Kuo. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49340 ) Change subject: mb/google/dedede/var/magolor: Enable EC keyboard backlight ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49340/comment/0efaf4f8_e59cda21 PS1, Line 10: TEST=emerge-dedede coreboot chromeos-bootimage Did you ensure that the keyboard backlight is turned on? -- To view, visit https://review.coreboot.org/c/coreboot/+/49340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f741da4a22494883939c4efe7960c66e71c6a7 Gerrit-Change-Number: 49340 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quantatw.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 17:38:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: Prevent NULL pointer dereference
by Paul Menzel (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: John Zhao, Angel Pons, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49359 ) Change subject: soc/intel/braswell: Prevent NULL pointer dereference ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf Gerrit-Change-Number: 49359 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 17:34:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/braswell: Prevent NULL pointer dereference
by Tim Wawrzynczak (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: John Zhao, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49359 ) Change subject: soc/intel/braswell: Prevent NULL pointer dereference ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf Gerrit-Change-Number: 49359 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 17:23:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/*: drop UART pad configuration from common code
by build bot (Jenkins) (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Karthik Ramasubramanian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48829 ) Change subject: soc/intel/*: drop UART pad configuration from common code ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/common/block/uart/uart.c: https://review.coreboot.org/c/coreboot/+/48829/comment/bad8a92f_55fc9d0d PS11, Line 59: if (CONFIG_UART_FOR_CONSOLE > uart_devices_size) Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/c/coreboot/+/48829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Gerrit-Change-Number: 48829 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 17:06:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/*: drop UART pad configuration from common code
by Michael Niewöhner (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Michael Niewöhner, Karthik Ramasubramanian. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Benjamin Doron, Paul Menzel, Subrata Banik, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Lance Zhao, Nico Huber, Martin Roth, Tim Wawrzynczak, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48829 to look at the new patch set (#11). Change subject: soc/intel/*: drop UART pad configuration from common code ...................................................................... soc/intel/*: drop UART pad configuration from common code UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Since all boards do pad setup on their own now, finally drop the pad configuration from SoC common code. Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/uart.c M src/soc/intel/apollolake/uart.c M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/Kconfig M src/soc/intel/common/block/uart/uart.c M src/soc/intel/elkhartlake/uart.c M src/soc/intel/icelake/uart.c M src/soc/intel/jasperlake/uart.c M src/soc/intel/skylake/uart.c M src/soc/intel/tigerlake/uart.c 12 files changed, 55 insertions(+), 340 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/48829/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/48829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Gerrit-Change-Number: 48829 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/braswell: Prevent NULL pointer dereference
by Arthur Heymans (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: John Zhao, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49359 ) Change subject: soc/intel/braswell: Prevent NULL pointer dereference ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf Gerrit-Change-Number: 49359 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 16:52:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2021